NVIDIA GEForce 8800 Architecture Quiz
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Questions and Answers

What type of instructions does the processor implement?

  • String manipulation instructions
  • 32-bit and 64-bit integer arithmetic only
  • IEEE 754 standard double precision floating point operations
  • PTX instructions for parallel thread execution (correct)

What is the purpose of GPU processor's multithreading according to the text?

  • To execute vector instructions efficiently
  • To increase power consumption
  • To reduce the number of available threads
  • To hide memory access latency (correct)

Which type of operations are included in the processor's capabilities?

  • Only single precision floating point operations
  • All PTX instructions and 32-bit integer arithmetic (correct)
  • Only logical instructions
  • 64-bit integer arithmetic and string operations

What distinguishes earlier GPUs from later GPUs regarding instruction execution?

<p>Later GPUs designed to execute ordinary scalar instructions (B)</p> Signup and view all the answers

What is a key goal achieved by the GPU processor's multithreading according to the text?

<p>Hiding memory access latency (D)</p> Signup and view all the answers

In what way does multithreading benefit the processor according to the text?

<p>Supports fine-grained parallel programming by allowing thread switching during waits (C)</p> Signup and view all the answers

How much total memory is available in the NVIDIA GEForce 8800?

<p>768 MB (C)</p> Signup and view all the answers

What is the peak bandwidth of the NVIDIA GEForce 8800 in GB/second?

<p>86.4 (B)</p> Signup and view all the answers

How many streaming multiprocessors are there in the NVIDIA GEForce 8800?

<p>14 (C)</p> Signup and view all the answers

What type of processor is a core in the NVIDIA GEForce 8800?

<p>Multithreaded processor supporting 96 threads (B)</p> Signup and view all the answers

How many scalar 32-bit registers are contained in the register file for the threads in the NVIDIA GEForce 8800?

<p>1024 (A)</p> Signup and view all the answers

Which unit in the NVIDIA GEForce 8800 integrates a shared geometry controller and a shared texture unit and cache?

<p>Texture/processor cluster (TPC) (D)</p> Signup and view all the answers

How many threads are distributed among 8 cores in a warp?

<p>32 threads (D)</p> Signup and view all the answers

What does the GPU's multiprocessor do to execute different thread programs concurrently?

<p>Virtualizes physical processors as threads and thread blocks (A)</p> Signup and view all the answers

How many CUDA cores are there in the Fermi based GPU architecture?

<p>512 CUDA cores (B)</p> Signup and view all the answers

How does each thread in the GPU multiprocessor achieve independence during execution?

<p>Possesses private registers, memory, program counter, and execution state (A)</p> Signup and view all the answers

In how many clock cycles will a warp of 32 threads execute one instruction each?

<p>4 clock cycles (D)</p> Signup and view all the answers

What simplifies the parallel programming model in CUDA extensions to C and C++?

<p>Writing serial kernel functions (B)</p> Signup and view all the answers

How many warps can be scheduled on a single Tesla using fine-grained multithreading over time?

<p>24 warps (D)</p> Signup and view all the answers

What components make up each SP core in the multithreaded multiprocessor architecture?

<p>Numerical arithmetic units, Shared memory, Read-only constant cache (A)</p> Signup and view all the answers

How many transistors are implemented in the Fermi based GPU architecture?

<p>3.0 billion transistors (B)</p> Signup and view all the answers

What is the role of the Multithreaded instruction unit in a GPU multiprocessor?

<p>Executing most instructions in an SP core (C)</p> Signup and view all the answers

How many SMs are there in the Fermi based GPU architecture?

<p>16 SMs (C)</p> Signup and view all the answers

How do threads within a thread block in a GPU multiprocessor synchronize with each other?

<p>Using a barrier synchronization instruction (D)</p> Signup and view all the answers

What is the benefit of running two warps in parallel?

<p>Increases efficiency in memory accesses (B)</p> Signup and view all the answers

How many warp schedulers does each SMX have in the Kepler architecture?

<p>Four (A)</p> Signup and view all the answers

What happens if threads of a warp diverge via a data-dependent conditional branch?

<p>Threads will converge back to the same execution path (D)</p> Signup and view all the answers

In SIMT architecture, what is the ideal scenario for warp efficiency?

<p>All 32 threads of a warp agree on the execution path (C)</p> Signup and view all the answers

When does branch divergence occur?

<p>Only within a warp (C)</p> Signup and view all the answers

How many instructions per warp can be dispatched per cycle in the Kepler architecture?

<p>Two (A)</p> Signup and view all the answers

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