Multi-Core Architecture and Parallel Computing

Multi-Core Architecture

• Multi-core processors integrate two or more independent processing units (cores) on a single chip to improve performance and energy efficiency.
• Key features include shared resources (caches, memory controllers, or buses), core communication (shared-memory or message-passing), and power efficiency (lower clock speeds for cores reduce heat generation).
• Multithreaded applications and virtualization are common applications.

Parallel Computing

• Parallel computing is a computational model where multiple processes or threads execute simultaneously to solve problems faster.
• Types of parallelism include data parallelism (same operation on multiple data elements) and task parallelism (different tasks executed concurrently).
• Models of parallelism include shared memory (all processors share a single address space, requiring synchronization to avoid data races) and distributed memory (each processor has its memory, communicating via message passing, used in clusters or supercomputers).
• Key challenges are load balancing, data synchronization, and communication overhead.

Branch Prediction

• Branch prediction reduces control hazards by guessing the outcome of branch instructions (e.g., if-else, loops) before they are resolved.
• Techniques include static prediction (always predict "taken" or "not taken") and dynamic prediction (using historical data to predict outcomes).
• Examples include 1-bit predictors, 2-bit predictors, branch target buffers (BTBs), and global history registers (GHRs).
• Speculative execution involves executing instructions based on predictions; if wrong, the pipeline is flushed.

Cache Optimization

• Cache is a small, fast memory located close to the processor to reduce access time for frequently used data.
• Key optimizations include cache hierarchies (L1, L2, L3 caches), associativity (direct-mapped, set-associative, and fully-associative), write policies (write-through or write-back), and prefetching.
• Block size, replacement (LRU, random, FIFO), miss types (compulsory, conflict, capacity) are vital.

Pipeline

• Pipelining is a technique used in processors to increase instruction throughput by overlapping instruction execution.
• A typical pipeline has stages like instruction fetch, decode, execution, memory access, and write-back.
• Hazards in pipelines include structural hazards (hardware resource limitations), data hazards (instruction dependencies), and control hazards (branch instructions).
• Solutions include forwarding, stalls, reordering, branch prediction, and pipeline flushing.

Instruction-Level Parallelism (ILP) & Superscalar

• ILP is the extent to which multiple instructions can be executed simultaneously, exploiting parallelism in program code.
• Key techniques include pipelining, superscalar execution (multiple functional units executing instructions in parallel), out-of-order execution (reordering instructions), and speculative execution.
• Superscalar processors can execute more than one instruction per clock cycle.

Cache Parameter Questions

• Doubling line size halves the number of tags in the cache because more data can fit per line.
• Doubling associativity does not change the number of tags in a cache.
• Doubling cache capacity in a direct-mapped cache usually decreases conflict misses as it increases the number of lines.
• Doubling cache capacity in a direct-mapped cache does not reduce compulsory misses.
• Doubling the cache line size will not change compulsory miss rate, or the number of misses.

This quiz explores the concepts of multi-core architecture and parallel computing. You'll learn about the features of multi-core processors, the types of parallelism, and the various models of computation that enhance performance and efficiency. Test your knowledge on these essential topics in modern computing.