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What is a limitation of a bus-based multiprocessor system?

  • It cannot connect multiple CPUs.
  • It uses a complex architecture for memory access.
  • It requires each CPU to have its own private memory.
  • Bus contention can become a bottleneck. (correct)

    • How do local memory systems help improve efficiency in multiprocessors?

  • By providing each CPU with its own private memory. (correct)
  • By increasing the amount of data each CPU must share.
  • By eliminating the need for any shared memory.
  • By requiring more complex programming models.

    • What distinguishes multicomputers from multiprocessors?

  • Each CPU in multicomputers has its own private memory. (correct)
  • Multicomputers rely on shared memory for communication.
  • Multicomputers connect CPUs with a single shared bus.
  • They require fewer processors to operate effectively.

    • What is a key benefit of hybrid systems in computing?

    <p>They provide a simpler programming model without high costs.</p> Signup and view all the answers

    What term do some computer scientists prefer to use instead of 'memory'?

    <p>Store or storage</p> Signup and view all the answers

    Why is a bit considered an essential unit of memory?

    <p>It holds a value of either 0 or 1.</p> Signup and view all the answers

    What is the role of memory in digital computers?

    <p>It stores programs and data for processors to use.</p> Signup and view all the answers

    What is a potential downside of many CPUs accessing shared memory in a multiprocessor system?

    <p>Potential for bus contention issues.</p> Signup and view all the answers

    What was the primary focus of RISC architecture?

    <p>Simple instructions that execute quickly</p> Signup and view all the answers

    What was a significant disadvantage of complex instruction sets in CISC architectures such as VAX?

    <p>They often resulted in slower execution for complex instructions.</p> Signup and view all the answers

    Which of the following best characterizes a RISC architecture?

    <p>It uses a small number of instructions that are executed directly by hardware.</p> Signup and view all the answers

    What led to the initial popularity of interpreter-based designs in computing in the 1970s?

    <p>The ability to add new instructions easily</p> Signup and view all the answers

    Why did CISC architectures maintain dominance in the market despite RISC's advantages?

    <p>Legacy software investments created a barrier for switching to RISC.</p> Signup and view all the answers

    Which of the following is a core design principle of modern computers related to RISC?

    <p>Direct hardware execution of common instructions</p> Signup and view all the answers

    How did Intel respond to the competitive landscape between RISC and CISC architectures?

    <p>By adopting a hybrid approach with RISC features in CISC architecture.</p> Signup and view all the answers

    What was the intended outcome of the RISC design philosophy?

    <p>Faster execution by simplifying instruction complexity.</p> Signup and view all the answers

    What was the purpose of the Red Book Standard for CDs?

    <p>To ensure cross-compatibility among different CD players.</p> Signup and view all the answers

    Which of the following statements about CD-ROM data organization is true?

    <p>A CD-ROM formats data into 98-frame sectors.</p> Signup and view all the answers

    Which development by Philips and Sony introduced enhanced error correction for CD-ROMs?

    <p>Yellow Book</p> Signup and view all the answers

    What is the main reason computers use binary for data encoding?

    <p>It minimizes errors by distinguishing just two values.</p> Signup and view all the answers

    How many combinations can a 16-bit Binary system represent?

    <p>65,536 combinations</p> Signup and view all the answers

    What capability did the Green Book introduce for CDs?

    <p>Interleaving audio and multimedia data in the same sector.</p> Signup and view all the answers

    Which feature distinguishes Mode 1 CD-ROMs from Mode 2?

    <p>Mode 1 provides enhanced error correction.</p> Signup and view all the answers

    What is the purpose of memory addresses in a computer?

    <p>To identify specific memory locations for program access.</p> Signup and view all the answers

    If a memory system has 12 cells, what is the minimum bit address required?

    <p>4-bit address</p> Signup and view all the answers

    In BCD (Binary Coded Decimal), how many bits are needed to represent one decimal digit?

    <p>4 bits</p> Signup and view all the answers

    Which of the following best defines 'Big Endian' byte ordering?

    <p>Bytes are numbered starting from the high-order end.</p> Signup and view all the answers

    How many unique addresses can a memory address with 5 bits represent?

    <p>16 unique addresses</p> Signup and view all the answers

    What is the relationship between the number of bits in a memory address and the amount of data stored per cell?

    <p>They are completely unrelated.</p> Signup and view all the answers

    What is the minimum Hamming distance required to correct a single-bit error?

    <p>3</p> Signup and view all the answers

    What does a parity bit ensure regarding the data?

    <p>The total number of 1s is either even or odd.</p> Signup and view all the answers

    Given the codewords with a Hamming distance of 5, how many single-bit errors can be corrected?

    <p>2 errors</p> Signup and view all the answers

    Which type of parity ensures the total number of 1s is even?

    <p>Even parity</p> Signup and view all the answers

    If a code can detect up to 4 single-bit errors, what is its Hamming distance?

    <p>5</p> Signup and view all the answers

    What is the formula to determine the minimum number of check bits needed?

    <p>m + r + 1 ≤ 2r</p> Signup and view all the answers

    How many total differences are there between the codewords 0000000000 and 1111111111?

    <p>10 differences</p> Signup and view all the answers

    Which code type can only detect single-bit errors but does not provide correction?

    <p>Single parity bit</p> Signup and view all the answers

    What is the primary purpose of RAID technology?

    <p>To enhance disk performance and reliability</p> Signup and view all the answers

    Which RAID level is known for its high fault tolerance due to data mirroring?

    <p>RAID Level 1</p> Signup and view all the answers

    What is the main characteristic of RAID Level 0?

    <p>Data is split into strips and distributed</p> Signup and view all the answers

    What limitation does RAID Level 3 have compared to other RAID levels?

    <p>It can only handle one I/O request at a time</p> Signup and view all the answers

    How does RAID Level 5 improve upon RAID Level 4?

    <p>It distributes parity information across all disks</p> Signup and view all the answers

    Why was there a need to transition from floppy disks to modern storage media?

    <p>Floppy disks have become obsolete and are rarely used</p> Signup and view all the answers

    What performance drawback is associated with RAID Level 4?

    <p>Bottleneck due to the dedicated parity disk</p> Signup and view all the answers

    Which RAID level utilizes Hamming code for error correction?

    <p>RAID Level 2</p> Signup and view all the answers

    Study Notes

    Introduction

    • This chapter introduces the three primary components of a digital computer: processors, memories, and input/output (I/O) devices.
    • These components form an interconnected system fundamental to computer architecture.
    • The chapter provides a foundational overview before delving into more detailed discussions in following chapters.

    Processors

    • Figure 1 depicts the organization of a simple computer with one CPU and two I/O devices.
    • The CPU acts as the "brain" of the computer, fetching, decoding, and executing instructions stored in memory.
    • The CPU's control unit fetches instructions, and the arithmetic logic unit (ALU) performs operations.
    • The CPU has high-speed internal memory called registers, including the Program Counter (PC) and Instruction Register (IR), crucial for managing instruction execution.

    1.1 CPU Organization

    • A typical von Neumann CPU includes a data path consisting of registers, the Arithmetic Logic Unit (ALU), and buses connecting them.
    • Registers transfer data to the ALU, which performs operations like addition and subtraction. Results are stored in output registers.
    • Two main types of instructions are register-memory and register-register.
    • Register-memory instructions move data between memory and registers, while register-register instructions operate on values in registers.
    • The data path cycle, processing operands through the ALU and storing the result, is central to CPU performance.

    1.2 Instruction Execution

    • Instruction execution in a CPU follows a fetch-decode-execute cycle.
    • Instructions are fetched from memory, decoded, and executed.
    • The process can be performed by hardware or software interpreters.
    • Software interpreters simplify and reduce hardware costs by executing instructions.

    1.3 RISC vs CISC

    • In the late 1970s, experimentation with complex instructions led to two competing CPU design philosophies: RISC (Reduced Instruction Set Computer) and CISC (Complex Instruction Set Computer).
    • RISC, pioneered by John Cocke at IBM, focused on simple, quickly executed instructions, emphasizing instruction throughput rather than complexity.
    • CISC architectures, like the DEC VAX and IBM mainframes, had larger instruction sets and more complex operations.

    1.4 Design Principles of Modern Computers

    • Modern computer design principles, often called RISC design principles, focus on efficiency and performance.
    • Direct Hardware Execution: Common instructions are directly executed by hardware, enhancing speed. Complex instructions are broken into smaller parts for occasional use.
    • Maximizing Instruction Issuance: The goal is to issue as many instructions per second as possible, utilizing parallel processing.
    • Easy Instruction Decoding: Instructions have a regular, fixed length with few fields, simplifying decoding and enhancing execution.
    • Memory Access via Loads and Stores: Only LOAD and STORE instructions directly access memory, minimizing delays.
    • Abundant Registers: Plenty of registers allow efficient use of fetched data without constantly reloading from memory, boosting performance.

    1.5 Instruction-Level Parallelism

    • Instruction-level parallelism (ILP) improves performance by executing multiple instructions in parallel within a single CPU.
    • Pipelining: Instructions are divided into stages handled by separate hardware units. This allows multiple instructions to be processed concurrently in different stages.
    • Superscalar Architecture: Multiple pipelines or functional units issue and execute multiple instructions per cycle (e.g. Intel Pentium). Compatible instructions can be executed in parallel to increase throughput.

    1.6 Processor-Level Parallelism

    • Achieving significantly higher performance involves increasing instruction-level parallelism, including pipelining and superscalar processing methods.
    • Array Processors: Highly effective for structured, regular computations, like performing the same calculations on multiple data sets simultaneously. These systems are designed for parallel execution. Single Instruction Multiple Data (SIMD) architecture broadcasts instructions to all processors for parallel execution.
    • Vector Processors: Processor uses a single, pipelined adder performing operations on pairs of data from vector registers.
    • Multiprocessors: Multiple independent CPUs sharing a common memory for tightly coupled operation. Bus-Based Multiprocessors: CPUs connect to a shared memory via a single bus. Bus contention can be a bottleneck when many processors access shared memory simultaneously.
    • Multicomputers: For larger systems, shared memory architectures can become impractical. Each CPU has its own private memory, and CPUs communicate via messages in multicomputers.
    • Hybrid Systems: Combine multiprocessor and multicomputer benefits for ease of programming in shared memory systems without increased complexity and cost of shared memory architectures.

    2.1 Bits

    • A bit is the basic unit of computer memory. It stores a value either 0 or 1.
    • Binary Efficiency: Binary (0 and 1) minimizes errors, as there are only two values to distinguish. Information is stored in physical variations. Fewer values means greater reliability. Binary is the most stable method for encoding digital data.
    • Binary Coded Decimal (BCD): Large computers use BCD to store decimal numbers; each decimal digit is represented by four bits.

    2.2 Memory Addresses

    • Memory is organized into cells or locations, each with a unique number – an address.
    • Programs access memory locations using addresses. For n cells, addresses can range from 0 to n-1.
    • Each cell contains the same number of bits, denoted as k. So it can store 2^k possible combinations for a given bit length. m-bit addresses can be used to access up to 2^m cells directly.

    2.3 Byte Ordering

    • Bytes in a word can be numbered from left-to-right (big-endian) or right-to-left (little-endian).
    • Big-endian format stores the most significant byte (MSB) at the lowest memory address.
    • Little-endian format stores the least significant byte (LSB) at the lowest memory address.

    Error-Correcting Codes

    • Computer memories experience errors from voltage spikes.
    • Error-correcting codes (ECC) add redundancy to memory words to detect and correct errors.
    • A memory word consists of m data bits and r check bits, creating a total length of n=m+r. An n-bit unit is a codeword.
    • Hamming distance between two codewords is the number of positions where the corresponding bits differ (using XOR).
    • To detect d single-bit errors, a code needs a Hamming distance of d+1.
    • To correct d single-bit errors, a code needs a Hamming distance of 2d+1.
    • A parity bit ensures the total number of 1s in data is either even or odd for simple error detection. It cannot perform correction.

    3.1 Memory Hierarchies

    • CPU registers are the fastest, smallest storage, accessed at full CPU speed.
    • Cache memory is larger than registers, holds frequently accessed data, providing faster retrieval. Access times are slightly slower than registers.
    • Main memory holds a large amount of data and programs. Access times are in the range of tens of nanoseconds.

    3.2 Memory Hierarchies

    • Magnetic disks are the primary means for permanent storage, storing many gigabytes. Access times are measured in milliseconds.
    • Magnetic tape and optical disks are used primarily for archival storage with slower access times. Capacity is limited by budget.

    3.3 Magnetic Disks

    • A magnetic disk is a storage device composed of coated platters, and writes/reads data by magnetizing areas on the platter's surface.
    • Tracks are circular sequences of bits; sectors have 512 bytes of data each.
    • Components include preambles (for synchronization), data, and ECC (error correction).
    • A disk arm moves to access distinct circular tracks (concentric circles).
    • Zone Bit Recording: outer zones have more sectors for increased capacity.
    • Perpendicular Recording increases data density. Winchester disks are sealed to protect surfaces.

    3.4 Floppy Disks

    • IBM invented floppy disks mainly for mainframe maintenance. They quickly became popular for personal computer software distribution.
    • Floppy disks are physically flexible; unlike hard disks, floppy disk heads touch the surface for storage.
    • Due to the direct surface contact, there is more media and head wear compared to hard disks.
    • Floppy disks are no longer common, as modern computers generally don't include floppy disk drives.

    3.5 RAID

    • RAID stands for Redundant Array of Independent Disks.
    • RAID addresses slow disk performance by using multiple drives in parallel.
    • SLED vs RAID: Single Large Expensive Disk and RAID disk use multiple disks which appear as a single disk to the OS. RAID levels 0-5 are illustrated in Figure 2-23.

    3.6 CD-ROMS

    • Optical disks became popular due to high capacity and lower costs, initially for TV recording.
    • Examples include LaserVision and Audio CDs. The Compact Disc (CD) became the first mass-market digital storage, published as the Red Book Standard..
    • CD-ROM use a Pit-Land structure using a low power laser to read pits (depressions) and lands (flat areas). Binary data is distinguished by the transition points.
    • Error handling and correction were improved and standardized for reliable encoding with the Yellow Book standard in 1984.. Data is organized into 98-frame sectors, each containing 16 byte preamble, 2048 data, and 288 byte ECC code. The format supports Modes 1 and 2 for enhanced error correction (usually for audio) and data merging and interleaving (typical graphics and multimedia, especially in 1986 and later media formats).

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