MOSFET Level 1 Model

MOSFET Level 1 Model

• Referred to as the Shichman-Hodges model.
• Simplest of the four MOSFET models in SPICE.
• Accurate only for long channel devices.

DC Model

• Threshold voltage Vth calculation for the SPICE Level 1 model:
  • Vth = VTO + γ(√(2Φf + VSB) - √(2Φf))
    • VTO: Zero-bias threshold voltage of a long channel device.
    • γ: Body factor.
    • Φf: Bulk Fermi potential.
    • VSB = 0V
    • No short channel or narrow width effects are accounted for.
• Saturation voltage Vdsat calculation:
  • Vdsat = Vgs - Vth
• Drain current Ids calculation:
  • Linear region: Ids = βo[(Vgs - Vth)Vds - (Vds²/2)](1 + λVds) where Vgs > Vth and Vds ≤ Vdsat
  • Saturation region: Ids = 0.5βo(Vgs - Vth)²(1 + λVds) where Vds > Vdsat
  • Subthreshold region: Ids = 0 where Vgs ≤ Vth
  • βο = κ(W/L) and κ = µoCox
  • λ: channel length modulation factor for continuous current and derivative in linear/saturation regions.
  • Subthreshold current is zero.
• Models the source/drain (S/D)-to-substrate pn junctions.
• Only DC parameter of the S/D junction of interest is the saturation (leakage) current Is, since the junctions are reverse biased during normal operation.
  • In SPICE, this is specified as Js.
    • Js: Saturation current per unit area
    • Is: Total saturation current.
  • If Js is specified, the source and drain areas As and Ad must be specified.

Capacitance Model

• Parameters of the dynamic model: include source/drain junction capacitances, overlap capacitances, and intrinsic MOSFET capacitances.
• Junction capacitances are the sum of bottom-wall (area) capacitance and side-wall (periphery) capacitance.
• Source diode capacitance CBS calculation:
  • CBS = (CjoAs) / (1 - (Vs / Φb))^mj + (CjswPs) / (1 - (Vs / Φb))^mjsw
  • As and Ps: Area and periphery of the source-to-bulk pn junction.
  • Cjo and Cjsw: Junction capacitance per unit area and per unit periphery at zero back bias.
  • Similar equation calculate Drain-to-bulk junction capacitance CBD
• Intrinsic device capacitances (gate oxide capacitances) are based on the Meyer model.
  • Three intrinsic capacitances in the Meyer model: CGS, CGD and CGB.
  • Values change with bias conditions.

Strong Inversion Region

• Region defined by when Vgs > Vth,
• Gate capacitance equations:
  • Linear Region: Vgs > (Vth + Vds)
    • CGS = (⅔) * Coxt * [1 - ((Vgd - Vth)² / (Vgd + Vgs - 2Vth)²)]
    • CGD = (⅔) * Coxt * [1 - ((Vgs - Vth)² / (Vgd + Vgs - 2Vth)²)]
    • CGB = 0
  • Saturation Region: Vth < Vgs < (Vth + Vds)
    • CGS = (⅔) * Coxt
    • CGD = 0
    • CGB = 0

Weak Inversion Region

• Region defined by Vgs < Vth, divided into two parts in SPICE
• Transition between saturation and weak inversion regions is made linear.
• Gate capacitance equations:
  • When (Vth - Φf) < Vgs < Vth:
    • CGS = (⅔) * Coxt * [(Vgs - Vth) / Φf + 1]
    • CGD = 0
    • CGB = Coxt * [1 + (4(Φsb - Vsb) / Φf)]^(-½)
  • When Vgs < (Vth - 2Φf ):
    • CGS = 0
    • CGD = 0
    • CGB = Coxt
• Overlap capacitances CGSO, CGDO and CGBO are added to CGS, CGD and CGB, respectively, in different regions of device operation.
  • CGSO = cgso * W
  • CGDO = cgdo * W
  • CGBO = cgbo * L

SPICE Level 1 Model Parameters:

• VTO: Zero-bias threshold voltage [V]
• KP: Transconductance parameter [A/V²]
• GAMMA: Body factor
• UO: Low field mobility [cm²/V-s]
• PHI: Surface potential in strong inversion [V]
• LAMBDA: Channel length modulation factor [V⁻¹]
• NSUB: Substrate doping [cm⁻³]
• TOX: Gate oxide thickness [m]
• NSS: Surface state density [cm⁻²]
• TPG: Type of the gate material
• JS: Bulk junction saturation current [A/m²]
• RS: Source ohmic resistance [Ω]
• RD: Drain ohmic resistance [Ω]
• RSH: Source/drain diffusion sheet resistance [Ω/Π]
• CBS: Zero-bias B-S junction capacitance [F]
• CBD: Zero-bias B-D junction capacitance [F]
• CJ: Zero-bias bulk junction capacitance [F/m²]
• MJ: Bulk junction bottom grading coefficient
• PB: Bulk junction potential [V]
• CJSW: Zero-bias bulk junction sidewall capacitance [F/m]
• MJSW: Bulk junction sidewall grading coefficient
• CGSO: Gate-source overlap capacitance [F/m]
• CGDO: Gate-drain overlap capacitance [F/m]
• CGBO: Gate-bulk overlap capacitance [F/m]
• KF: Flicker noise coefficient
• L: Drawn channel length (mask dimensions) [m]
• W: Drawn channel width (mask dimensions) [m]
• AS: Source diffusion area [m²]
• AD: Drain diffusion area [m²]
• PS: Perimeter of the source diffusion window [m]
• PD: Perimeter of the drain diffusion window [m]
• NRS: Number of squares in the source diffusion
• NRD: Number of squares in the drain diffusion
• Electrical parameters will always override values computed from process parameters
• If VTO, NSUB, and TOX are input, the threshold voltage takes the VTO value, and GAMMA is computed from NSUB and TOX.
• If KP is not specified but UO is, KP is computed with the specified TOX value or its default if not specified
• If VTO is not an input parameter, NSUB, TOX, and TPG are needed to calculate VTO.

Parameter TPG

• TPG denotes the gate type with three possible values:
  • +1: gate type opposite to the substrate
  • -1: gate type same as the substrate
  • 0: aluminum gate

Model Parameter Determination

• All Level 1 parameters determined except KP and LAMBDA.
• LAMBDA: Saturation region parameter, found from the slope of Ids vs. Vds curve in saturation.
• KP: Determined either from the slope of the linear region plot of Ids vs. Vgs at low Vds, or from the slope of √Ids versus Vgs curve (Ids in saturation region).

MOSFET Level 2 Model

• Incorporates many second-order effects for small size devices.
• Can model a reasonable range of device sizes.
• Computationally complex.

DC Model

• Threshold voltage equation for the SPICE Level 2 model:
  • Vth = VTO - γ√(2Φf) + γF√(2Φf + VSB) + Fw(2Φs + VSB)
    • F₁: Short channel factor.
    • Fw: Narrow width factor.
    • περεσι Gw / 4 Cox W
• Linear Region Current:
  • Ids = βeff [(Vgs - Vth - ½Vds) Vds - F₁{(Vds + 2Φf + Vsb)^(3/2) - (2Φf + Vsb)^(3/2)}]
    • βeff = (κ µs W) / (µo Left)
    • V*th = VTO - γ√(2Φf) + Fw(2Φs + Vsb)
    • με = µo / [1 + θ(Vgs - Vth)]
    • η = 1 + Fw
    • Leff = L(1 - γVds)
    • Lm: Drawn channel length.
    • Ldif: Side diffusion.
    • Channel length modulation (CLM) factor λ is used.

Saturation Voltage

• Saturation voltage Vdsat can be calculated in one of two ways:
  • If maximum carrier drift velocity Umax is assumed zero.
• Vdsat using the pinch-off model:
• Vdsat = (Vgsx - Vth) / η [(1 + (γFi) / η)² - 1 + ((γFi) / η)√(1 + 4((Vgsx - Vth + 2Φf + Vsb) / η))]^(½) - V*gsx: min(Vgs, Vth)

Vdsat using the velocity saturation model:

• Calculated using the Baun and Benking model:
  • Idsat = Umax Qsat W
    • Idsat = βeff [(Vgs - V*th - ½Vdsat) Vdsat - (⅓) γF₁((Vdsat + 2Φf + Vsb)^(3/2) - (2Φf + Vsb)^(3/2))]
    • Qsat = Cox[Vgs - V*th - ηVdsat - γF₁(√(Vdsat + 2Φf + Vsb))]
    • Umax = (µs[(Vgs - Vth - 0.5ηVdsat)^2 - ⅓ γF₁((Vdsat + 2Φf + Vsb)^(3/2) - (2Φf + Vsb)^(3/2))]) / (Leff[Vgs - Vth - ηVdsat - γF₁(√(Vdsat + 2Φf + Vsb))])
    • V₁ = (Vgs - V*th) / η + 2Φf + Vsb
    • V₂ = 2Φf + Vsb
    • µ = (Umax L) / µs
    • X = √(Vdsat + 2Φf + Vsb) Equation (11.27) is solved for X using Ferrari's method.

Leff Calculation

• Leff = L(1 - λVds)
• Depends upon whether the CLM term λ has a finite value.
  • If λ = 0, then Leff = L.
  • If λ is not input then it is calculated internally.
    • If Umax ≤ 0, Vdsat is calculated using pinch-off model, and effective channel length evaluated using: λ = (Xd / (LVds)) * {(Vds / Vdsat) + √(1 + ((Vds - Vdsat) / 4)^(½))} where Xd

Xd = √(2εsiΦb / qNb)

• If Umax > 0, then Vdsat is calculated using Eq. (11.26d), and λ is given by = (Xd / (LVds)) * {(µeff Umax Xd² / (2µs Vds)) + ((Vds - Vdsat) / 2µs)^(½)} where Xd = √(2εsi/ qNbNeff)

Saturation Region Current

• In this region, Vds > Vdsat
• Current calculated using Eq. (11.20) with Vds replaced by Vdsat.

Subthreshold Current

• Current in the subthreshold region is calculated using:
• Ids = Io exp[q(Vgs - Von)/(nkT)]
• n = 1 + (qNfs / Cox ) + (Cd / Cox) + Fw
• Cd = (dQb / dVbs) * γFi√(2Φf + Vsb)

SPICE Level 2 Model Parameters

• LD: Lateral diffusion [m]
• DELTA: Narrow width factor
• XJ: Junction Depth [m]
• UCRIT: Critical field for mobility degradation [V/cm]
• UTRA: Mobility transverse field coefficient
• UEXP: Exponent in mobility degradation
• VMAX: Maximum carrier drift velocity [m/s]
• NEFF: Effective substrate doping factor
• NFS: Fast surface state density [cm⁻²]
• XQC: Thin-gate oxide capacitance model

MOSFET Level 3 Model

• Semi-empirical model that includes second order effects due to short-channels and narrow-widths.
• Computationally efficient compared to the Level 2 model.
• Empirical model parameters become geometry dependent.

DC Model

• Threshold voltage equation for the SPICE Level 3 model:
• Vth = VTO - γ√2Φf + γF√2Φs + Vsb + Fw(2Φs + Vsb) - σVds
  • F₁: Short channel factor based on Dang's model.
  • Fw: Narrow width factor as in Level 2.
  • σ : DIBL parameter.
  • σ= (8.15 * 10^-22*η) / (CoxL^3)

Linear Region Current

• The drain current, Ids, in the linear region is given by
  • Ids = β(Vgs - Vth - ½Vds) Vds
    • β = κ (µeff W) / (µo L)
    • µeff = µo / [1 + (µoVds / Umax L)] -µeff = µo/[1 + θ(Vgs - Vth)]
    • α = 1 + (γFi / 4√(2Φf + Vsb)) + Fw If the parameter Umax is not specified, µeff is set to µs and the velocity saturation effect is not modeled.

Saturation Voltage

• Vdsat is calculated from one of the following equations:
  • Vdsat = (Vgs - Vth + (Umax L / µs) / α ) -√((Vgs - Vth +(Umax L / µs))^2 / α - ((Umax L / µs)^2 / α ^2))
  • (if Umax specified)
  • Vdsat = (Vgs - Vth) / α (if Umax not specified).

Saturation Region Current

• The drain current, Ids, in the saturation region is calculated using
  • Ids = Idsat / (1 - (la / L))
    • la= κ √((X²(Vds - Vdsat) + ((Xd²GP / 2) )^2) - ((Xd^3 GP)/2)^2)
    • Xd = √((2εsi/ qN)
    • Gdsat = (dIdsat/ dVdsat)
    • Gdsat = GP/L
• Subthreshold Region Current: It is given by the same equation as for the Level 2 model but Ids calculated using Eq. (11.35).
• The SPICE Level 3 DC model parameters are in addition to the Level 1 parameters, except for the parameter LAMBDA
• Usually, the value of VMAX is 3-5 times higher than the physical value.

empirical parameter DEL

• Introduced so that Eq. (11.36b) reads
• ueff = Mo / [1 + (DEL * Vds / Lo max)]

Table 11.8. SPICE Level 3 Model Parameters

• LD: Lateral diffusion
• DELTA: Narrow width factor
• XJ: Junction Depth [m]
• NFS: Fast surface state density [cm⁻²]
• THETA: Mobility degradation factor [V⁻¹]
• ETA: Static feedback factor
• KAPPA: Saturation field correlation factor
• VMAX: Maximum carrier drift velocity