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Computational Model and Architecture

• A program is a static sequence of high-level statements, broken down into simple, structured instructions.
• The CPU manipulates instructions and data to perform computations.
• Program execution is a dynamic process, defined by the flow of instructions.
• Instruction flow is the continuation of executed instructions—the path taken in the code.
• Control flow is the succession of path selections during execution.
• Data flow is the path data takes during execution.
• The control mechanism specifies how execution occurs and how one instruction leads to another.
• In control-driven execution, an instruction is executed when the control flow selects it.
• In data-driven execution, a statement executes when all its arguments are available.
• Demand-driven execution means an instruction runs if its result is needed by another instruction already executing.
• Pattern-driven execution relies on the correspondence of certain patterns or goal statements.
• The data mechanism specifies how an instruction gets its operands and how results are communicated.
• Shared memory means the main memory stores a single copy of information, shared and accessed by reference.
• Message passing involves sending a copy of operands to each unit for computation; data access is by value.
• A computation model is a high-level abstraction explaining how computations are carried out, including entities, operations, and execution/data models.
• The Turing model can be used to determine whether a function is computable.
• The object-oriented model uses objects containing attributes and methods.
• The Dataflow model uses data-driven execution with message passing, where instructions produce data for other instructions.
• The Application model uses arguments as entities to which functions are applied for evaluation.
• The Predicate logic-based model is based on a set of objects to which predicates (properties) are applied, and uses pattern-driven execution and shared data.

Architecture in Computer Systems

• Computation models rely on computer architecture and programming languages.
• Main language types are procedural, object-oriented, functional, and logical.
• "Architecture" refers to system attributes visible to the programmer. It is based on the computation model and programming languages used.
• Architecture also refers to the study and classification of computers.
• The semantic gap is the difference between the High-Level Programming Language's (HLL) computation model and the architecture required to execute them.

Architecture Models

• The original von Neumann architecture is the foundation of current processors, enhanced with features like pipelines, cache memory, and prefetching.
• It involves a procedural problem description model with instructions executed on a data flow.
• It involves a centralized execution model based on state transition semantics.
• It features a unique stream of instructions executed on data stored in memory (single-instruction stream).
• The modern von Neumann model has been extended for additional high-level language functionality and greater speed.
• The concept of stacking encapsulates recursion in computation.
• New data types include binary coded decimal, fixed/floating-point real numbers, and character strings.
• It employs complex addressing modes like indexing and indirection.
• Tables are used with pointers and dynamic entities.
• Increased memory capacity utilized virtual memory mechanisms such as paging and segmentation.
• Parallel computation was introduced by multiplying functional units and implementing pipeline structures.
• In a pure Harvard architecture, code and data are stored in two distinct memories, each with its own communication path to avoid access conflicts.
• Each memory has its own communication path (bus).
• Parallelism is intrinsic since each address corresponds to multiple storage locations.
• Modified Harvard architectures mix von Neumann and Harvard architectures.
• Unified memory and specialized memory closer to the processor (cache) are used to improve flow rates.
• In that model, address zero refers to a single memory cell, but instructions and data communications use separate buses.

Parallelism

• Parallelism is a computing method where parts of a complex task are split up and run simultaneously on multiple CPUs.
• Instruction-Level Parallelism refers to how many operations are performed simultaneously by the program.
• Instruction-level parallelism brings together design techniques from processors and compilers to overcome sequential execution.
• It speeds up instruction execution, especially data transfers and arithmetic operations.
• Thread-Level Parallelism allows a program or instruction to work in multiple threads.
• It is referred to as multithreaded parallelism, with two approaches: explicit and implicit multithreading.
• Explicit Multithreading (Chip Multithreading) involves issuing instructions from multiple threads in a cycle.
• Hardware Multithreading involves having multiple thread contexts in a single processor.
• Fine-grained multithreading provides two or more threads in a chip.
• Coarse-grained multithreading provides multiple threads within a processor core.
• Hyperthreading transforms parallelism at the activity thread level into parallelism at the instruction level.
• Chip Multiprocessing replicates an entire processor core for each thread in order to support multiple threads on a processor chip.
• Implicit Multithreading generates threads by the hardware or compiler.

Multicore Architecture

• A multicore microprocessor consists of multiple independent cores on the same die (single-chip multiprocessor).
• When the number of cores is very high, the terms many-core and massively multicore are used.
• Each core is pipelined and has multiple levels of cache.
• Symmetric Multiprocessing consists of identical cores sharing memory.
• Asymmetric Multiprocessing uses cores with different capabilities.

Instruction Set Architecture (ISA)

• This is the architecture of the processor seen by the programmer and is the interface between software and hardware.
• An instruction set defines operations, instruction format, coding, addressing modes, and the number, type, and size of operands.
• The processor executes in different modes: application-level, system-level, and supervisor modes.
• Storage components consist of general-purpose registers, main memory, and the stack.
• In a register-register architecture, only load and store instructions access memory.
• In a memory-memory architecture, all operands are in memory with a potentially large instruction size.
• Various instruction sets are used in the industry and are of theoretical importance.
• Reduced Instruction Set Computer (RISC) has fewer cycles per instruction (CPI).
• Complex Instruction Set Computer (CISC) requires fewer instructions per program than RISC.
• Minimal Instruction Set Computer (MISC) has a very small number of instruction operations and opcodes.
• Very Long Instruction Word (VLIW) is designed to exploit instruction-level parallelism.
• Explicitly Parallel Instruction Computing (EPIC) allows processors to execute software instructions in parallel, controlled by the compiler.
• One Instruction Set Computer (OISC) uses only one instruction, eliminating the need for an opcode.
• Zero Instruction Set Computer (ZISC) uses pattern matching without traditional instructions.
• Basic examples of instructions are: LOAD for retrieving data, STORE for saving data, OUT for outputting, IN for inputting, ADD for summing, COMPARE for comparisons, and JUMP for directing flow.

Bus Interfaces and Classifications

• Bus nodes are either masters (M) or slaves (S), such as MPUs, memory devices, or I/O controllers.
• The bus interface facilitates communication between modules.
• A clocked interface relies on a clock signal for pacing and timing.
• Functional modules manage bus access, arbitration, interruptions, and DMA transfers and generate bus timing signals.
• Signals on a bus differ from power supply lines and carry information.
• Logical signals are active on a high/low state or on signal edges.
• Bus signals are independent of the electrical interface and microprocessor protocol.
• Bus signals are separated into families based on function.
• An address transfer bus carries addresses from master to slaves.
• A data transfer bus carries data (n signals) and can handle smaller words.
• A control bus consists of access control signals, including memory and I/O operations. The status bus reports bus errors.
• An access arbitration bus manages access to transfer buses.
• A synchronization bus carries clock signals.
• A utility bus generates start/stop sequences.
• Interfacing logic isolates and amplifies signals, shifts voltage levels, and uses drivers and receivers.
• The communication path in a bus is a transmission line, characterized by resistance, inductance, capacitance, and conductance per unit length.
• Noise influences the signal and leads to transmission errors, including crosstalk between lines.
• Noise sources include RFI (Radio-Frequency Interference) and EMI (Electromagnetic Interference).
• Shielding protects against electromagnetic interference.
• Propagation times are on par with signal periods, requiring careful management of clock signals.

Architectural Implementations

• Initially, all entities shared a single bus (the shared bus).
• Segmented buses consist of portions allowing communication between masters and slaves.
• Hierarchical buses have clusters communicating through a locally segmented bus, then a global bus.
• Multiple buses allow concurrent communication, and can be implemented hierarchically.
• A Bridge links two buses electrically.
• A Local bus is at the component level on the PCB, it is the bus of the microprocessor.
• Memory buses are used in memory systems, with a controller managing multiple ranks of memory over several channels.
• Link buses connect microprocessors or bridges and use packets for communication.
• Expansion slot buses have connectors for I/O interface cards and expansion cards.
• Expansion buses allow a baseboard to have its own small I/O expansion board; it is board-level bus.
• I/O buses link one or more devices to one or several I/O controllers, such as those for mass storage (ATA, SCSI).
• Backplane and centerplane buses connect electronic cards using printed circuit boards.
• Fieldbus implements programmable logic controllers (PLCs), interacting with instruments, sensors, and actuators.
• A SoC (System on a Chip) integrates components (microprocessors, memories, I/O controllers) down to a single chip.
• Power bus supplies power to a computer system with precise voltages.