Mixed Signal IPs in Deep Submicron Technologies

Industrial Aspects of Analog Design in Deep Submicron Process Technologies

• This is Lecture 2, Weeks 2 and 3 and overviews IPs DDR, PCle, USB-C, UCIe, Ethernet, DP, HPMI, PLL, and Vreg
• What is out there in the market for an analog and Mixed Signal designer is explored
• High level block diagrams, specs, KPIs and compliance with focus on design challenges of these Mixed Signal IPs

Mixed Signal IPs, What is Done

• Memory interfaces include DDR and LPDDR
• High Speed I/O covers USB, PCI Express, Thunderbolt, and SATA
• MIPI includes DPHY and CPHY
• Ethernet covers 10G KR, 25G, 56G, and 100G
• Display Interface includes DP, eDP, DSI, and HDMI
• On Package IO includes UCIe, R-Link
• Also: PLL, GPIO, Voltage Regulator & Security (RNG)

Defining IPs

• Many IPs provide the physical interface from silicon to the outside world
• The PHY interfaces the board and the controller
• The interface between the PHY (PCS layer) and the controller is well defined, providing a good boundary point to the IP

Standards & Technology Roadmaps

• Data Rate & Protocol Version
• Product/Platform Needs:
  • Protocols Needed
  • Power Management
  • Power Delivery
• Competitive Analysis:
  • Power
  • Area
  • Latency
  • Speed
• User Experience/Complexity of integration
• Example USB Type C:
  • Standards: USB 3.1, TBT 3.0, DP1.3 -> Frequency of operation of 20 G
  • Optimization BOM -> SOC integration
  • Aggressive power management
  • Defining power delivery in CPU for such PHY
  • Competitive analysis -> What is best in class?

IP Components

• Analog Front End contains all the analog/circuit blocks
• Digital Front End is used to call also RX/TX dig, micro partition
  • It is the logic that control the analog blocks (calibration, adaption)
  • Highly dependent on the architecture and analog implementation
• PCS stands for physical coding sublayer
  • It usually contains the encoding and buffering
  • Logic block

IP Design Flows

• IPs generally have three main design flows: Analog, Custom Logic, and Synthesized Logic
• Example of SERDES Receiver containing Analog, Custom Logic & Logic

Must-Knows

• System analysis
• Analog design
• Custom Layout
• Logic design
• Logic flow (timing, synthesis, P&R)
• RV flows
• DFX
• Validation with Logic, Analog, & Mixed Signal
• Post Silicon Validation
• High volume manufacturing

Analog Design Flow

• Architecture, which includes the architecture solution, system analysis, and tech readiness (TR)
• Implementation, with circuit and layout with layout flows as DRC, LVS, and DFM
• Validation including pre/post layout simulation, performance mixed-signal, EOS, aging, Monte-Carlo
• Failure in each step can impact completed steps behind and require redo
• Experience and high quality conclusion of the architecture step will reduce redo and ensures fast convergence

Digital Design Flow

• Architecture solution, system analysis and tech readiness (TR)
• Implementation including RTL coding, Synthesis, Place & Route, Layout flows (DRC, LVS, DFM)
• Logic validation, functional mixed-signal, GLS
• Failure in each step can impact the completed steps behind and require redo & experience and high quality conclusion of the architecture step will reduce redo and fastest convergence

IP1 to PRQ – IP Point of View

• Architecture: IP1 is defining spec targets and early path finding; IP2 is final Feature Definition and Tech Readiness; IP3 is config, that fits IP2 envelope, Schedule, and cost commits
• Design: RTL 0.5 is Partial feature coding/Limited validation; RTL 0.8 is 100% feature coded/Limited validation
• Implementation: RTL 1.0 is 100% validation/Only bug fixes from RTLOP8; POLO is post layout extracted views; PROD is Final GDS for tape-in
• Validation: IPES1 is ES1 ready/Post-si val in process; IPES2 is HVM ready/Post-si val complete
• Key IP milestones align with product requirements & Full feature (spec) definition in the planning phase allows predictable implementations

Product Stepping & Testchip

• Target for B0 PRQ
• Testchip will require full design cycle
• If testchip is not full content of the IP, a full cycle will be done towards A0, which usually require parallel work on the testchip and A0

What's needed to start

• Feature definition - from the product including the landing zone
• Platform definition involving supply voltages and channels
• Process definition including devices, transistor types, resistors, Capacitors
• Collateral to support the design flows: Libraries & process files

Change Considerations

• Changes can be mainly caused by a new feature request (PCR – Product Change Request) or process or collaterals changes
• Late changes add iteration to the design cycle and in extreme cases major redo

Team Interaction

• Tech Dev which includes Process technology devices and features
• EDA involving Flows and tool development
• Controller with Soft IP which interacts with hard IP (in many case - the controller), requiring close interaction is required to allow sub-system validation
• Product team with Feature definition & Product requirements
• High Vol involving Post Si validation

Desktop Computer I/O Architecture

• High-speed I/O interfaces exists
• Key bandwidth bottleneck points are FSB or memory and graphics interfaces which are PCI
• Near-term architectures includes integrated memory controller with serial I/O (>5Gb/s) to memory and increasing PCle from 2.5Gb/s (Gen1) to 8Gb/s (Gen3)
• Other serial I/O systems such as Multi-processor systems & Routers

Chip to Chip Signaling Trends

• 1980's: Lumped capacitance, >10Mb/s speeds and Inverter out/in Transceiver Features
• 1990's: Transmission line, >100Mb/s speeds and Termination/Source-synchronous clk. Transceiver Features
• 2000's: Lossy transmission line, >1 Gb/s speeds and Pt-to-pt serial streams/Pre-emphasis equalization Transceiver Features
• Future: >10 Gb/s speeds, Adaptive Equalization, Advanced low power clk. & Alternate channel materials Transceiver Features

High-Speed Electrical Link Systems

• Basic diagram of electrical link system including TX data, Serializer, ref clock , RX clock, Deserializer, Transmission line
• Timing diagram of the link systems and dependency

Channel Performance

• Graphics representing channel & pulse responses, & eye diagrams for Desktop Channel, Refined BP Channel & Legacy BP Channel

Interface Data

• Data on USB, SATA, Display Port, QPI, PCle, XAUI
• USB Data Rates: 1.5Mbs, 12Mbs, 480Mbs, and 5Gbs; Medium: 12" FR4, 5 m cable & 3 m cable; Coupling DC; Coding Bit Stuff; Clock Embedded No SSC/SSC;
• SATA Data Rate: 1.5Gbs, 3Gbs, & 6Gbs; Medium: 6" FR4 & 1 m cable; Coupling AC,DC; Coding 8b/10b ; Clock Embedded SSC;
• Display Port Data Rate: 1.62Gbs & 2.7Gbs; Medium: 10" FR4 & 3 m cable(?); Coupling AC; Coding 8b/10b
• QPI Data Rate: 6.4Gbs & 8Gbs; Medium: 20"FR4 & 2 Connectors ; Coupling DC; Coding None; Clock Forward
• PCle Data Rate: 2.5Gbs, 5Gbs, 8Gbs; Medium: 20"FR4 & 2Connectors ; Coupling AC; Coding 8b/10b & 128b/130b; Clock Embedding No indep SSC;
• XUAI Data Rate: 3.125Gbs; Medium: 20"FR4 & 2Connectors ; Coupling AC; Coding 8b/10b; Clock Embedding No SSC;

Definitions

• Channel is a Interconnect between two devices such as Package, FR4, Connectors, Cables
• Insertion Loss is the Loss of Signal Power from one end of the channel to the other, usually measured in dB where S21 = 20*Log(Vout/Vin)
• Return Loss is the Loss of Signal Power due to a discontinuity or termination, usually measured in dB where RL = S11 = 20Log(Vrefl/Vin), Vrefl = ΓVin, Γ = Reflection Coefficient = (Zrx - Zo)/(Zrx+Zo) where S11 = 20*Log(|Γ|)
• Inter Symbol Interference is "Smearing" of one bit symbol into others which is Primarily due to Frequency Dependent Loss and Wave Velocity
• De-emphasis, Pre-emphasis and Tx Equalization helps to reduce ISI effects on longer interconnect, they are basically the same thing where Pre-emphasis makes the initial bit(s) after a transition larger than nominal while de-emphasis makes the subsequent bits after a transition smaller than nominal. (Larger and smaller refer to amplitude.) These are a subset of Tx Equalization: Multi (> 2) Tx levels dependent on data pattern (FIR Filter). It looks at the bits already sent and subsequent bits to be sent to determine the amplitude.
• Spread Spectrum Clocking (SSC:)is a low frequency (~33KHz) modulation of the reference clock frequency (for EMI "reduction"). Some interfaces (SATA) support independent SSC for each device, others (PCI Express, QPI) support SSC from a common clock reference with both devices modulate together, however others don't support SSC, where IA systems, SSC generally "downspreads" the frequency by 5000ppm
• BER a measure of the Bit Error Rate and and how often an error occurs on the link, with a standard target is 10-12 l.e. 1 error in 1012 bits, so for a 2.5Gbs lane, 1 error occurs in 400 sec (6.67 min), and with this there has to be an error recovery mechanism such as 8b/10b code errors detected, CRC checks on the data and Re-send the data if there's an error if there's an error
• The Eye Diagram, thought of as an infinite persistence O'scope capture which needs the appropriate "reference" to trigger on, and is is Used to determine effective Data eye width and height, and May have some SW filtering applied

USB3 Mobile Channel Insertion Loss

• -23dB loss at 2.5GHz, so a 1V transmitted signal will arrive with only 71mV amplitude
• Loss Delta between 500MHz and 2.5GHz is ~17dB
• Lowest frequency “bits” are 5.6x larger amplitude than high frequency bits
• Transmit Equalization is -3.5dB thus Receive side equalization is required

PHY Functional Block Diagram

• Phy includes Transmitters(Tx) covering PISO, Pre-driver, Driver, De-emphasis, Termination
• Receivers(Rx) covering Diff-amp, Squelch, Termination, Sampling Flops, Clock/Data Recovery Circuit (CDR) & SIPO
• Clocks with PLL(s), Clock Distribution, Clock Muxing
• Common to All Transceivers on the Interface(s) where itMay contain precision reference (Band Gap),Resistor Comp (Rcomp) & Current Comp (Icomp)
• PHY also includes Phy Coding Sub-Layer, a Phy logical control and PIPE Interface to the controller, configureation registers, and more

High Speed Serial IO

• Overview of components and basic diagram including a Driver, Transmitter EQ, Data Eye & Receiver components, key challenges are:
  • High data rates => SATA gen3 is 6Gbs; PCIe gen2 and USB3 are 5Gb/s
  • Lossy channels => PCI e channels are up to 20″ long; USB3 channels can be 14" of FR4 and 3m of cable with USB3 as a closed Rx eye spec
  • Clock must be recovered from the incoming data and then centered in the middle of the eye to capture data Represents an issue as a Recovered clock freq may be offset from local clock due to Spread Spectrum Clock

Challenges

• Challenge #1* – High Data Rate and Lossy Channel
• Graphics show TX Data & EQ and eye diagrams for receiver input and corresponding frequency
• Challenge #2* - Clock and Data Recovery from Closed Eye
• Graphics show TX Data & EQ and recovered data and corresponding frequency

Elements of Serial I/O

• Signaling
  • How the symbol is transmitted from one end to another
  • Current mode vs. voltage mode in TX
  • Single ended vs. differential
• How the line is terminated at TX & RX ends?
  • Source or end termination or Both
• Signal corruption sources (Voltage Noise)
  • Crosstalk
  • ISI
  • Power supply noise
  • Thermal noise
  • Statistical parameter variation (offset)
• On-chip and off-chip signaling
  • TX & RX Equalization
• Synchronization: -How & when to decide on the correct RX signal value? Synchronous timing where all signals share single clock, which has Major Skew & Jitter Issues limited to small range of frequencies

Elements of Serial

• Synchronisation
• Pipeline timing: Forward Clock with signal with a wide range of operating frequency with Skew & Jitter limit max frequency

Elements of Serial

• Synchronization
• Closed Loop timing: Measures & compensate skew has a more complicated design that Requires PLL analysis being Bundled vs. per-line closed-loop architecture Sources of timing errror with Ideal Diagram with timing errors

Elements of Serial

• Power distribution
• Sources of power Supply Noise: Supply voltage error having a di/dt effect as anEffect of R, L and C & inductive Supply Noise for effective on and off Chip Bypassign & Power Supply Regulation

Interconnect Model

• Propagation Equation that assumes infinitely long T-Line with no reflection
• Constant α as Attenuation is Frequency & Material dependent:
  • Skin effect (R term)
  • Dielectric loss (G term)
• Constant β where Phase is proportional to velocity is Frequency & Material dependent & Assuming small losses (R&G term)

Channel Pulse Response vs. Data Rate

• 25% Eye Opening @ 5Gb/s*(Best case assumptions) or more realistically
• 10% Eye Opening @ 10Gb/s*(Best case assumptions) or more realistically
• 50% Eye Opening @20Gb/s*(Best case assumptions)or more realistically

NEXT vs. FEXT

• Next: Large TX signals leaking on to a nearby RX with small remote signals, cable cross talk increases, beyond X frequency power interference equals signal power
• FEXT: signal leakage to faraway RX with local Tx interfering signal, interfering & desired signals are cable attenuated & is ALWAYS dominated in limiting performance

Transmit Data Equalization (Also Known As Pre-Emphasis

• isolated bits or rapidly alternating 0/1s Don't build on receiver side, requires full lossy channel
• Equalization & adjustment of output based on input
• reduces maximum swing

RX Equalization Noise Enhancement

• Linear RX equalizers don't differentiate input sources SNR is unchanged though signal & distortion improves