Merged Exams for PDP Midterm Quiz

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Questions and Answers

What is the purpose of microprocessor pipelining?

To allow multiple instructions to be processed sequentially.

To eliminate the need for cache memory.

To improve performance by concurrent instruction processing. (correct)

To reduce the complexity of instruction sets.

Which statement accurately describes the role of context switching?

Context switching involves concurrent execution of threads.

It helps in the management of memory caches.

It refers to the parallel processing of independent applications.

Context switching is the swapping of different applications in multitasking. (correct)

What is a consequence of dynamic instruction scheduling in VLIW machines?

Enhanced performance through static instruction control.

Reduced complexity in instruction fetching.

Improved ability to handle dependent instructions. (correct)

Increased dependency stalls in the pipeline.

What does a cache miss indicate?

The data requested is not found in the cache. Signup and view all the answers

In distributed-memory architecture, how do processors access memory?

Individually, without shared memory. Signup and view all the answers

Which statement about Level-2 cache (L2) is true?

It is smaller in data capacity than Level-1 cache (L1). Signup and view all the answers

What is critical path length used to represent in parallel computing?

The maximum time required to complete all tasks. Signup and view all the answers

Which characteristic is typical of multiprocessors?

They typically range from four to thirty-two processors. Signup and view all the answers

Which of the following statements about Level one cache (L1 cache) compared to Level two cache (L2 cache) is correct?

L1 cache is faster and closer to the processor than L2 cache. Signup and view all the answers

Which component is NOT included in the process state?

Physical Memory Addressing Signup and view all the answers

In parallel processing, which decomposition technique is likely to cause a slowdown under ideal conditions?

Exploratory Decomposition Signup and view all the answers

What technique is primarily used to reduce the overhead of interactions between concurrent tasks?

Overlapping Computation and Communication Signup and view all the answers

What is likely to decrease when the maximum degree of concurrency in a task graph increases?

Critical path length Signup and view all the answers

If the number of processors is increased to four in a parallel algorithm, what key metric would you expect to improve?

Maximum achievable speedup Signup and view all the answers

Which of the following is NOT a valid parallel processing algorithm for database enquiries?

Depth-First Search Algorithm Signup and view all the answers

In creating a Task Dependency Graph (TDG) for database processing, which is most important to consider?

Independent tasks without dependencies Signup and view all the answers

Which types of locality does cache support?

Temporal locality Signup and view all the answers

Which memory storage is faster than all the others?

Registers Signup and view all the answers

What is the term for when the CPU successfully finds the data in the cache?

Cache hit Signup and view all the answers

Data is typically moved from cache to memory in which manner?

One full block Signup and view all the answers

Which of the following describes parallel processing architectures?

Both B and C Signup and view all the answers

Cache coherency protocols can include which of the following strategies?

Both A and C Signup and view all the answers

In a Symmetric Shared Memory Multiprocessor, which type of memory access does it use?

Uniform Memory Access (UMA) Signup and view all the answers

What overhead does a parallel program incur based on interactions among processes?

All of the above Signup and view all the answers

Study Notes

Microprocessor Pipelining

Pipelining enhances performance by processing instructions concurrently in different stages.
Stalls in the pipeline occur when instructions have dependencies.
Stalling allows for simultaneous execution of multiple instructions across different Functional Units (FUs).
Dynamic Instruction Scheduling is not typically used in VLIW (Very Long Instruction Word) machines.
Superscalar processors utilize Static Instruction Scheduling to boost performance.

Cache Memory

Compilers do not have access to control data placement in the cache.
Special locality refers to the likelihood of reusing the same data soon, related to locality in time.
A Cache Miss occurs when the desired data is found outside the cache.
Level-1 cache (L1) has greater data capacity compared to Level-2 cache (L2).

Multiprocessing & Multithreading

Context switching involves swapping different applications during multitasking.
Threads from the same program do not share the same set of architectural registers.
Superscalar uni-processors experience both vertical and horizontal waste of issue slots.
Different threads or applications do not share CPU resources in multi-core processors.

Parallel Architecture

Multi-computers are interconnected through a network.
Distributed-Memory architecture does not allow uniform access to memory (not UMA).
Multiprocessors commonly consist of 4 to 32 processors.
The MPI (Message Passing Interface) is used for centralized memory architecture in parallel programming.

Analytical Model & Parallel Algorithms

Aggregate memory bandwidth drives superscaling in distributed parallel systems.
Parallel system efficiency can be one (1) but still not be cost-effective.
Critical Path length indicates the Time Parallel (Tp).
Level-1 cache (L1) is faster and closer to the processor compared to Level-2 cache (L2).

Process State

The process state includes architecture/logical registers, program counter, and memory space state.

Decomposition Techniques

Ideal parallel algorithm conditions can lead to slowdowns through various decomposition techniques including data, exploratory, and recursive decomposition.
Techniques to minimize concurrent task interaction overhead encompass data replication, optimized collective communication operations, and overlapping computation with interaction.

Cache Concepts

Registers are faster than Level-one cache (L1), Level-two cache (L2), and main memory.
Registers have less capacity than all forms of cache (L1, L2, and main memory).
A cache hit occurs when the CPU successfully finds requested data in the cache.
Data is transferred from the cache to memory in block sizes, not bit by bit or byte by byte.

Parallel Processing Categories

Parallel processing encompasses SISD (Single Instruction Single Data), MISD (Multiple Instruction Single Data), and MIMD (Multiple Instruction Multiple Data), with the latter two being part of parallel architectures.
Coherency protocols in caches include mechanisms for cache update and cache invalidate.
In Symmetric Shared Memory Multiprocessors, memory access is categorized under UMA (Uniform Memory Access) but can also imply aspects of NUMA (Non-Uniform Memory Access).

Interaction Overhead

Interaction overhead in parallel programs is influenced by data exchange volume, frequency of interaction, and spatial/temporal interaction patterns.

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Description

Test your understanding of microprocessor pipelining techniques and their impact on performance. This quiz covers various concepts such as stalls, instruction dependencies, and scheduling in VLIW and superscalar processors. Perfect for students learning about microprocessor architecture.