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Questions and Answers
What is the purpose of microprocessor pipelining?
What is the purpose of microprocessor pipelining?
- To allow multiple instructions to be processed sequentially.
- To eliminate the need for cache memory.
- To improve performance by concurrent instruction processing. (correct)
- To reduce the complexity of instruction sets.
Which statement accurately describes the role of context switching?
Which statement accurately describes the role of context switching?
- Context switching involves concurrent execution of threads.
- It helps in the management of memory caches.
- It refers to the parallel processing of independent applications.
- Context switching is the swapping of different applications in multitasking. (correct)
What is a consequence of dynamic instruction scheduling in VLIW machines?
What is a consequence of dynamic instruction scheduling in VLIW machines?
- Enhanced performance through static instruction control.
- Reduced complexity in instruction fetching.
- Improved ability to handle dependent instructions. (correct)
- Increased dependency stalls in the pipeline.
What does a cache miss indicate?
What does a cache miss indicate?
In distributed-memory architecture, how do processors access memory?
In distributed-memory architecture, how do processors access memory?
Which statement about Level-2 cache (L2) is true?
Which statement about Level-2 cache (L2) is true?
What is critical path length used to represent in parallel computing?
What is critical path length used to represent in parallel computing?
Which characteristic is typical of multiprocessors?
Which characteristic is typical of multiprocessors?
Which of the following statements about Level one cache (L1 cache) compared to Level two cache (L2 cache) is correct?
Which of the following statements about Level one cache (L1 cache) compared to Level two cache (L2 cache) is correct?
Which component is NOT included in the process state?
Which component is NOT included in the process state?
In parallel processing, which decomposition technique is likely to cause a slowdown under ideal conditions?
In parallel processing, which decomposition technique is likely to cause a slowdown under ideal conditions?
What technique is primarily used to reduce the overhead of interactions between concurrent tasks?
What technique is primarily used to reduce the overhead of interactions between concurrent tasks?
What is likely to decrease when the maximum degree of concurrency in a task graph increases?
What is likely to decrease when the maximum degree of concurrency in a task graph increases?
If the number of processors is increased to four in a parallel algorithm, what key metric would you expect to improve?
If the number of processors is increased to four in a parallel algorithm, what key metric would you expect to improve?
Which of the following is NOT a valid parallel processing algorithm for database enquiries?
Which of the following is NOT a valid parallel processing algorithm for database enquiries?
In creating a Task Dependency Graph (TDG) for database processing, which is most important to consider?
In creating a Task Dependency Graph (TDG) for database processing, which is most important to consider?
Which types of locality does cache support?
Which types of locality does cache support?
Which memory storage is faster than all the others?
Which memory storage is faster than all the others?
What is the term for when the CPU successfully finds the data in the cache?
What is the term for when the CPU successfully finds the data in the cache?
Data is typically moved from cache to memory in which manner?
Data is typically moved from cache to memory in which manner?
Which of the following describes parallel processing architectures?
Which of the following describes parallel processing architectures?
Cache coherency protocols can include which of the following strategies?
Cache coherency protocols can include which of the following strategies?
In a Symmetric Shared Memory Multiprocessor, which type of memory access does it use?
In a Symmetric Shared Memory Multiprocessor, which type of memory access does it use?
What overhead does a parallel program incur based on interactions among processes?
What overhead does a parallel program incur based on interactions among processes?
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Study Notes
Microprocessor Pipelining
- Pipelining enhances performance by processing instructions concurrently in different stages.
- Stalls in the pipeline occur when instructions have dependencies.
- Stalling allows for simultaneous execution of multiple instructions across different Functional Units (FUs).
- Dynamic Instruction Scheduling is not typically used in VLIW (Very Long Instruction Word) machines.
- Superscalar processors utilize Static Instruction Scheduling to boost performance.
Cache Memory
- Compilers do not have access to control data placement in the cache.
- Special locality refers to the likelihood of reusing the same data soon, related to locality in time.
- A Cache Miss occurs when the desired data is found outside the cache.
- Level-1 cache (L1) has greater data capacity compared to Level-2 cache (L2).
Multiprocessing & Multithreading
- Context switching involves swapping different applications during multitasking.
- Threads from the same program do not share the same set of architectural registers.
- Superscalar uni-processors experience both vertical and horizontal waste of issue slots.
- Different threads or applications do not share CPU resources in multi-core processors.
Parallel Architecture
- Multi-computers are interconnected through a network.
- Distributed-Memory architecture does not allow uniform access to memory (not UMA).
- Multiprocessors commonly consist of 4 to 32 processors.
- The MPI (Message Passing Interface) is used for centralized memory architecture in parallel programming.
Analytical Model & Parallel Algorithms
- Aggregate memory bandwidth drives superscaling in distributed parallel systems.
- Parallel system efficiency can be one (1) but still not be cost-effective.
- Critical Path length indicates the Time Parallel (Tp).
- Level-1 cache (L1) is faster and closer to the processor compared to Level-2 cache (L2).
Process State
- The process state includes architecture/logical registers, program counter, and memory space state.
Decomposition Techniques
- Ideal parallel algorithm conditions can lead to slowdowns through various decomposition techniques including data, exploratory, and recursive decomposition.
- Techniques to minimize concurrent task interaction overhead encompass data replication, optimized collective communication operations, and overlapping computation with interaction.
Cache Concepts
- Registers are faster than Level-one cache (L1), Level-two cache (L2), and main memory.
- Registers have less capacity than all forms of cache (L1, L2, and main memory).
- A cache hit occurs when the CPU successfully finds requested data in the cache.
- Data is transferred from the cache to memory in block sizes, not bit by bit or byte by byte.
Parallel Processing Categories
- Parallel processing encompasses SISD (Single Instruction Single Data), MISD (Multiple Instruction Single Data), and MIMD (Multiple Instruction Multiple Data), with the latter two being part of parallel architectures.
- Coherency protocols in caches include mechanisms for cache update and cache invalidate.
- In Symmetric Shared Memory Multiprocessors, memory access is categorized under UMA (Uniform Memory Access) but can also imply aspects of NUMA (Non-Uniform Memory Access).
Interaction Overhead
- Interaction overhead in parallel programs is influenced by data exchange volume, frequency of interaction, and spatial/temporal interaction patterns.
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