Microcontroller Debugging Techniques

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Questions and Answers

What is a key limitation of using JTAG and Serial Wire Debug at the same time?

Serial Wire Debug does not support breakpoint features.

Both interfaces can operate simultaneously without issues.

JTAG is incompatible with Cortex-M processor-based devices.

Debugging in both modes at the same time is not possible. (correct)

Which unit allows you to set breakpoints while the processor is running?

Breakpoint Unit (correct)

Run Control Unit

Trace Port Interface

Memory Access Unit

What distinguishes the 4-Pin Trace Output from the Serial Wire Trace Output?

The 4-Pin Trace Output uses only 2 functional pins.

The 4-Pin Trace Output provides greater bandwidth. (correct)

The 4-Pin Trace Output does not output ETM trace data.

The 4-Pin Trace Output is used exclusively in JTAG mode.

Which component is used for instruction tracing and software profiling?

Embedded Trace Macrocell (ETM) Signup and view all the answers

What functionality does the Data Watchpoint & Trace Unit (DWT) provide?

Timing and interrupt execution information. Signup and view all the answers

What feature allows each interrupt to have its pending status set or cleared by software?

Flexible exception management Signup and view all the answers

How does the NVIC determine if a new exception should interrupt the current task?

By comparing priority levels Signup and view all the answers

Where is the vector table located after a system reset?

At address 0x0 Signup and view all the answers

What does the LSB of each exception vector indicate?

The execution state of the exception Signup and view all the answers

What is one function of the System Control Block (SCB)?

Providing fault status information Signup and view all the answers

Which type of exception has a fixed priority level?

NMI Signup and view all the answers

What does the vector table mechanism primarily determine?

The starting address of exception handlers Signup and view all the answers

What is a characteristic of nested exceptions in the NVIC?

They have variable priority levels Signup and view all the answers

What happens to the current value in the Link Register (LR) when a function call is made without proper handling?

It is lost. Signup and view all the answers

What does the Program Counter (R15) return when read?

The current instruction address plus 4. Signup and view all the answers

What is the purpose of special registers in the context of embedded OS development?

They facilitate interrupt masking features. Signup and view all the answers

Which of the following is true about the Execution Program Status Register (EPSR)?

It cannot be accessed by software code and reads as zero. Signup and view all the answers

What is the primary function of the Q flag in the Application Program Status Register (APSR)?

To signal sticky overflow for saturating instructions. Signup and view all the answers

The IPSR is designed to provide which type of information?

Interrupt or exception number. Signup and view all the answers

What does the 'T' bit in the EPSR indicate for Cortex M3 processors?

It should always be high. Signup and view all the answers

What role does the IT field play in the IT instruction statement?

It defines the number of subsequent instructions in the block. Signup and view all the answers

What architecture version is the ARM7TDMI based on?

ARMv4T Signup and view all the answers

What is a key feature of the Cortex Microcontroller Software Interface Standard (CMSIS)?

Facilitates software portability and reusability Signup and view all the answers

Which of the following is NOT typically included inside ARM microcontrollers?

External power supply Signup and view all the answers

What is the purpose of keeping the code inside an ISR short?

To minimize the time spent in the interrupt Signup and view all the answers

Which architecture version supports the Cortex-M processors?

ARMv7-M Signup and view all the answers

Which of the following statements is true regarding the use of Thumb instructions?

They reduce code size and improve performance. Signup and view all the answers

What is the primary function of the voltage regulator in ARM microcontrollers?

To provide stable power supply Signup and view all the answers

Which development suite is suggested for starting ARM microcontroller development?

STM32CubeIDE Signup and view all the answers

What is the primary purpose of the bit-band feature in the Cortex-M3?

To provide bit-level access to specific memory bits. Signup and view all the answers

Which of the following best describes 'bit-banging'?

Driving I/O pins under software control for serial communication. Signup and view all the answers

In the context of memory access attributes, what does cacheable refer to?

Data read can be stored in cache for faster access on subsequent reads. Signup and view all the answers

What does the term 'shareable' mean in memory access attributes?

The data in this memory region can be shared among multiple bus masters. Signup and view all the answers

What is a function of a boot loader in a microcontroller?

To provide a flash programming utility. Signup and view all the answers

What does memory remapping allow in a system with a boot loader?

Redirection of the boot loader to different memory addresses after initial startup. Signup and view all the answers

Which of the following is NOT a common memory access attribute?

Serializable Signup and view all the answers

Which statement is correct regarding exclusive access via MUTEX?

It prevents access to a resource by another thread until it is released. Signup and view all the answers

What must be true for an interrupt request to be accepted by the processor?

The pending status must be set and interrupt enabled. Signup and view all the answers

Where does the vector table typically start in memory by default?

0x00000000 Signup and view all the answers

What allows for the relocation of the vector table address in a Cortex-M processor?

Vector Table Offset Register (VTOR) Signup and view all the answers

What characteristic is NOT applicable to each interrupt?

Can only be pending or active. Signup and view all the answers

What feature does the Wake-Up Interrupt Controller (WIC) provide?

Detects external events to wake from power-down. Signup and view all the answers

Which statement about interrupt inputs in the NVIC is correct?

Interrupt inputs are active HIGH. Signup and view all the answers

What feature allows the Cortex-M to manage power effectively?

NVIC controls multiple sleep modes. Signup and view all the answers

What is meant by interrupt preemption?

Higher priority interrupt can interrupt a lower priority one. Signup and view all the answers

Which of the following is NOT a sleep mode supported by the Cortex-M3?

Infinite Sleep. Signup and view all the answers

What does clock gating primarily help to reduce?

Dynamic power dissipation. Signup and view all the answers

Study Notes

Introduction to ARM Cortex-M Processors

ARM Cortex-M processors are widely used, particularly in portable devices due to low power consumption and reasonable performance.
The course promises to save significant study time by providing a structured learning approach.
Daily 30-minute revisions of class material are encouraged for effective learning.

Course Content

Embedded software development and debugging using STM Cube IDE.
Mixed 'C' and Assembly coding.
Demystifying memory, bus interfaces, NVIC, and exception handling (with animations).
Low-level register programming for interrupts, system exceptions, setting priorities, and preemption.
IRQ handler, IRQ numbers, NVIC, and other OS-related features (e.g., SVC, SysTick, PendSV).

Cortex-M3 @ S/W Developer View

Programming Model (how exceptions are handled).
Memory Map.
Peripheral Interfacing.
Using software driver libraries from microcontroller vendors.
CMSIS Core API's.
STM32CUBE Libraries.

ARM Cortex-M Processors

The ARM Cortex-M3 & M4 processors are designed by ARM.
The first Cortex-M3 processor was released in 2005, the M4 processor was released in 2010.
32-bit architecture, with registers, data path, and bus interfaces all 32 bits wide.
The instruction set architecture (ISA) in the Cortex-M processors is called the Thumb ISA, based on Thumb-2 technology, and include 16- and 32-bit instructions.

ARM Cortex-M3 Microcontroller

18 x 32-bit registers
Excellent compiler target.
Reduced pin count requirements, efficient interrupt handling, and power management.
Efficient development support features (breakpoints, watchpoints, flash patch support, instruction trace).
Strong OS support and user/supervisor model.
OS support features, designed for full C programming(including resets, interrupts, and exceptions).

ARMv7M Architecture

No Cache - No MMU
Optimized for microcontroller applications
Vector table containing addresses (not instructions)
Interrupt handling, automatically saving/restoring state.
Exceptions programmed in C (no co-processor 15) - all registers are memory mapped.
Interrupt controller part of the Cortex-M3 macrocell.
Fixed memory map, bit-banding, and Non-Maskable Interrupt (NMI).

The Cortex M Processor Family

Scalable and compatible architecture.
Cortex-M0, M0+, M3, M4, and M7 processors.
Varying power efficiency, performance, code density, and features.

Advantages of Cortex-M Processors

Low power consumption (under 200 uA/MHz).
High performance (over 3 CoreMark/MHz & 1.25 DMIPS).
Energy efficiency.
Code density.
Ease of use (C friendly)
Scalability

Features Continued

Scalability.
Debug Friendly.
OS support.
Versatile system features (Bit-banding, MPU).
Software portability and reusability (CMSIS).

Architecture Versions and Thumb ISA

ARM7TDMI is based on ARMv4T (Thumb instruction support).
Architecture version 7.
Different profiles for Cortex-A, Cortex-R, and Cortex-M processors.

ISA Enhancement

Various architectures (v4/v4T, v5/v5E, v6, v7-A, v7-R, v7-M, v6-M).
Development of various ARM cores (ARM7TDMI, ARM926, ARM946,ARM966, IntelXScale, ARM1136, ARM1176, ARM1156-2, etc.)

Introduction to Embedded Software Development

Typical ARM microcontrollers and necessary components (development suits, boards, debugging tools, and documentation).
Software development flow (creating a project, adding files, setting up options, compiling and linking, flashing, testing, and debugging).
Software compiling flow (C source code, object files assembly, linker, executable image, utilities, debugger, hardware testing).

What is inside typical ARM microcontrollers

Processor takes a very small percentage of silicon area (less than 10%).
Program memory (e.g., flash memory), SRAM, peripherals, Internal bus infrastructure, clock generator, reset generator, and network, voltage regulator, power control circuits, other analog components (e.g., ADC, DAC, voltage reference circuits), and I/O pads.

Development Tools

Development suites (STM32CubeIDE).
Development boards (STM32F4 Discovery Board)
Debug Adaptor (STLinkv2)
Documentation and resources (links).

Software Development Flow

Detailed diagram demonstrates the steps involved in the software development process.

Software Compiling Flow

Diagram illustrating the steps in software compilation, including compilers, assemblers, linkers, and debuggers.

Polling Flow

Diagram outlining the sequence of operations (start, initialization checks, process request).

Interrupt-Driven Flow

Diagram showcasing the interrupt-driven process, starting with initialization and transitioning into sleep mode for processing after interrupt triggers.

Managing the ISR

Maintaining short and specific interrupt service routines (ISRs) for efficiency and reliability is critical. Minimizing instructions in an ISR reduces the chance of missed or dropped data and prevents conflicts with other interrupts.

Multitasking System

Real-time operating systems (RTOS) and their use in task scheduling enable concurrent execution of multiple processes, dividing the processor time into time slots and assigning them to specific tasks.

RTOS vs Superloop

Comparison of RTOS-based and standard superloop-based programming models.
RTOS-based programs exhibit more structure and concurrency, while the superloop approach provides a simpler programming environment.

ARM Data Size Definition

Byte definition (8-bit)
Half-word (16-bit)
Word (32-bit)
Double-word (64-bit)

Technical Overview

General information about ARM Cortex-M3 and M4 processors.
Processor Type.
Architecture.
Instruction Set.
Block Diagram.
Memory System, Interrupt and Exception Support.
Performance, Code Density, and Low Power.
Memory System and Protection Unit, Interrupt Handling, OS Support, Debug Support, Scalability, and Compatibility.

Processor Type and Architecture

32-bit RISC processors.
32-bit registers.
32-bit internal data path and bus interface.
3-stage pipelining (fetch-decode-execute).
Harvard Bus Architecture (simultaneous instruction and data access).

Instruction Set - Thumb2

High Performance
High Code Density
Variable-length instructions (16-bit and 32-bit).

The Thumb-2 instruction set

Variable-length instructions.
Improved code density and performance.
Supports both 16- and 32-bit instruction types.

ARM and Thumb Mode

The diagram illustrates the switching between ARM and Thumb instruction modes.
Overhead for switching from one mode to the other.
Design for optimizing either code size or performance.
Modern processors (e.g., ARM7TDMI) have better switching to leverage advantages of either approach.

Thumb2 No Switching Req.

Comparison of instructions sets and how modern processors typically do not include switching operations.

Block Diagram

Illustrative diagram showing the major components of a Cortex-M3/M4 processor integrated within a system.
Components include the 3-stage pipeline, floating-point unit, memory interface, interrupt controller, debug components, and debug access ports.

Various Bus Interfaces

Different bus interfaces such as I-CODE, D-CODE, System, PPB, and DAP for program, data access, and other internal/external communications.

AMBA System

A hierarchical system with different buses for high-performance ARM processors, internal RAM, DMA bus masters, and low-power peripherals.
Data and instructions are transferred simultaneously through AHB (high-bandwidth).

Memory Map

Simple linear memory map, partitioning memory space for instructions, data, Debug, peripherals, external RAM, external devices.

Memory System and Interrupt

Program memory (typically flash memory), data memory(typically SRAM), peripherals.
Nested Vectored Interrupt Controller (NVIC) for programmable interrupt handling.
Registers for memory mapping.

Features of Cortex M3

3-stage pipeline
Multiple bus interfaces, allowing simultaneous instruction and data access.
High clock frequencies.
Complex operations with reduced instructions.
Fetch capability - instruction fetches are 32-bit, most operations use 16-bit length.

Code Density

Thumb-2 technology for both 16- and 32-bit instructions.
Improved code density over ARM.

Low Power

Multiple sleep modes.
Integrated clock gating.
Optional advanced low power technologies (e.g., State Retention Power Gating).

Memory Protection Unit

Dividing memory space into regions and defining access permissions.
Exception handling when access rules are violated.

Interrupt Handling

Support for up to 240 interrupt inputs, NMI, and system exceptions.
Programmable priority levels for interrupts
Automatic interrupt/exception prioritization and handling.

STM32F4x Block Diagram

Illustrative diagram of the STM32F4x microcontrollers, depicting the architectural layout and connections.

Exception Types

Table of different exception type and priority levels in an ARM Cortex-M processor.

Interrupt Handling (Overview)

Flexible interrupt handling mechanisms.
Nested Interrupt handling and vector-based exception handling.
Interrupt masking and triggering functions and their importance.

Starting Address of Exceptions

Explanation of the Vector Table's mechanism to get exception handler addresses.
The table contains starting addresses, enabling access to exception handlers based on their type.

Vector Table

Table of different exceptions and related offsets in memory.
Use of least significant bit (LSB) for exception type in memory.

Fault Handling

System for handling various faults that might occur during execution.
Exception handling steps.
Debug support during development for analysis and correction of faults, if appropriate.

System Control Block (SCB)

A part of the processor integrated into NVIC dealing with configuration (e.g., low power mode) and fault status information.

CoreSight Debug and Trace

CoreSight features for debugging and tracing functionality on Cortex-M3/M4 processors.
JTAG and Serial Wire interfaces for debug mode operations.
Memory Access Unit for debugging, breakpoint unit for setting breakpoints.

CoreSight Features

JTAG and Serial-Wire interfaces for debugging
Debugging in JTAG and Serial Wire mode cannot be performed simultaneously.
Run Control to start, stop, and single-step operations.
Breakpoint Unit to set breakpoints while executing the code.
Memory Access Unit for memory reading and writing or peripheral access.
Trace ports, ETM, and DWT operations.

Debug Connections

Different connector and interfaces for debugging (e.g., JTAG, Serial Wire).

Trace Port Interface

Provides trace information using Serial Wire (SWO) and 4-pin trace output (more bandwidth).
Different internal components are involved in the trace-oriented functions (e.g., ETM, ITM, DWT).

Cortex Reset Sequence & Startup

Reset sequence details, including the following steps:
- Processor will be in thread mode and using the main stack.
- Core fetches MSP and PC from the vector table.
- All interrupts are disabled.
- Vector table contains valid values for NMI and hard error handler.
- Clearing PRIMASK, FAULTMASK and BASEPRI registers.
- Disabling MPU.
- Using Default memory maps.

Reset Behavior

Reset sequence and actions (loading MSP, loading reset handler vector address, and execution of reset handler).

Status of SP and PC during reset

How stack pointer (SP) and program counter (PC) are initialized after a processor reset. Depicting different sections and their allocation in memory.

Task to be Performed

Initializing/setting up the vector table (containing stack pointer and handler routines).
Configuring and enabling or disabling the NVIC.
Defining priorities among different interrupt requests.
SysTick Timer and ROM/RAM remapping.

Initialization Summary

Cortex-M series cores start up in Privileged, Thread mode, and how their modes work across various architectures.
Necessary configuration for initial setup and software initialization (e.g., MPU, enable interrupts, and remapping).

Memory System

4GB Linear address space for memory map and interactions.
Support for different endianness.
Bit Banding.
Write buffer (for faster writing performance).
Cache (for faster reading).
Executable code region.
Shareable memory region for multiple bus master operations.

Memory Map

Illustration and description of different memory sections (e.g., ROM, RAM, peripherals, special purpose registers etc.) of microcontroller design.

Memory Endianness

Big-Endian and little-Endian data formats.
Significance of bit order during data transfers.

Data Alignment and Unaligned data access

How data is stored, aligned in memory, and the implications for different data types.

Bit Banding

Efficient bit manipulation method suitable for embedded systems.
Describes memory regions used in the bit-banding operation.
Alias addresses to access individual bits.

Bit Access to Bit-Band region

Diagram illustrating the mapping between bit band and alias address locations.

Bit Band Mapping

Visualization of bit band mapping in different memory regions and their alias in terms of address.

Cortex-M3 Bit Banding

Calculation and formula for calculating a bit band alias given a bit. Memory location.

Cortex-M3 Bit Banding

Practical approach to write bit by bit and how the address translation happens via the cortex-M3 bus matrix.

Advantages of Bit-Band

Simplifying bit operations.
Provides optimized bitwise manipulatio.

Memory Access Attributes

Description of various attributes of memory region (e.g. bufferable, cacheable, executable, and shareable memory).

Exclusive Access via MUTEX

Accessing shared resources in a thread-safe manner.

Memory system in a microcontroller

How bootloaders affect the memory mapping.
Memory remapping (for reconfiguring address maps).

Bootloaders and Memory Remapping

How a boot loader in ROM can remap memory during the startup sequence.
Use cases for memory re-mapping.

Possibilities of Re-mapping

Potential for diverse memory mapping procedures, and whether additional configuration or addressing changes are required when booting an application.

Exceptions and Interrupts

Overview of different exception types, including their priorities and functions within a system.

Exceptions overview

Overview of different types, their handling, and how these mechanisms work within different types of exception scenarios.

Definitions of priority

Defines and distinctions of various definitions of priorities and how they are used in systems.

Interrupt inputs and pending behaviors

How different interrupt behaviors work and how the processor decides which events to process in order of priority.

Details of NVIC Registers for Interrupt control

Overview of the key registers involved in interrupt control, functionality, and how interrupts are managed and enable.

Summary of SCB registers

Summary of system control block registers, their functions, and their interplay with the overall system.

Exception Type

Defining and classifying each exception type and their role in exception handling.

Nested Vectored Interrupt Controller

Provides support for handling interrupts efficiently by using priorities and vector tables.

Vector Table Offset Register

VTOR register that can adjust the starting address of the vector table; making exceptional handling processes more portable across different architectures.

Vector Table Relocation

Explanation of the vector table relocation method in Boot ROM.

Booting from Pen Drive or SD

Detailed approach to booting from different external devices.

Interrupt Inputs and Pending behavior

Interrupt source and pending behavior to establish a framework for understanding different approaches.

Register in NVIC

Detailed description and function of each register within the NVIC (including enabling, disabling, setting priorities, and triggering interrupts); how interrupts can be managed.

Exceptions Handling In Detail

In-depth explanation of the exception handling processes, including details about handling exception entry, stacking/unstacking.

Exception sequence

Explanation detailing a framework for understanding complex exception sequences and their interactions with the overall system.

Nested Interrupt Stacking

Handling nested interrupts effectively.