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Microcomputer Systems Quiz

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76 Questions

What is the term for a collection of lines that connects several devices?

Bus

What are the components of a complete microcomputer system?

Microprocessor, memory, and peripheral equipment

What is another term for the PC Program Counter?

Instruction pointer

How many bits are in a single byte?

8

What operation does the CPU not perform?

Data transfer

What is the relationship between the access time of memory and the time required for performing a single CPU operation?

Longer than

What type of addressable memory refers to the successive memory words?

Word addressable

What is a microprogram written as a string of 0's and 1's?

Binary micro-program

What is the primary function of a control unit in the CPU?

To decode program instructions

What is a dedicated computer?

A computer assigned to one and only one task

What addressing technique is NOT employed by a CPU?

Relative

What is the purpose of a pipeline in a CPU?

To decode and execute instructions in stages

What code was developed by IBM Corporation?

EBCDIC code

Where is the address of the instruction following a CALL instruction stored?

Stack

What type of microprogram is written as a string of 0's and 1's?

Binary microprogram

What type of interrupt is initiated by an instruction?

Software

What type of architecture is defined by a single instruction that operates on multiple data elements?

SIMD (Single Instruction Multiple Data)

What is the maximum speedup that can be achieved according to Amdahl's law if 5% of a program is sequential and the remaining part is ideally parallel?

20

What type of hazard can be circumvented by register rotation in the Itanium processor?

Data hazards

Which type of MIMD systems are best scalable with respect to the number of processors?

Distributed memory computers

For which type of shared (virtual) memory systems is the snooping protocol suited?

Bus based systems

What is the key characteristic of SISD architecture?

Single instruction operating on single data element

What is the maximum number that can be stored in an 8-bit accumulator?

255

In a system with a 16-bit address bus, how many 1K byte memory devices can it contain?

256

What type of memory is volatile?

RAM

What is a peripheral?

Any physical device connected to the computer

How many bits are required to encode individual characters in Devanagari script?

10

What bus is used to transfer data from main memory to peripheral devices?

Data bus

What is created to provide increased memory capacity for an operating system?

Virtual memory

Which development led to the production of microcomputers?

Integrated Circuits

Who is NOT considered the inventor of the computer?

Alan Turing

What is the fastest storage unit in a typical memory hierarchy?

Register

Which type of cache miss does not occur in a fully associative cache?

Conflict miss

What type of miss even occurs in infinite caches?

Cold start miss

What is stored in a Translation Lookaside Buffer (TLB)?

Physical addresses

What is the speedup of a parallel program that achieves an efficiency of 75% on 32 processors?

24

What is the pipelining strategy implemented in?

Instruction prefetch

Which algorithm is a better choice for pipelining?

Merge-Sort Algorithm

Where does a copy of the instructions reside during execution?

Cache

What is the primary factor that determines the cost of parallel processing?

Circuit Complexity

Which instruction set architecture is characterized by one instruction per cycle?

RISC (Reduced Instruction Set Computer)

What is the term for a processor that can execute different instructions during the execution of another instruction?

Pipe-lining

In a daisy-chaining priority method, how are devices that can request an interrupt connected?

In serial

Which type of instruction set is characterized by variable format instructions?

CISC (Complex Instruction Set Computer)

Which processor executes an instruction with an average of 3 steps and has a clock frequency of 700 Mhz?

Processor A

Which type of parallel processing may occur in both the instruction stream and data stream?

Both in the instruction stream and data stream

What is the primary function of a control unit in the CPU?

To manage data transfer

What type of architecture is defined by a single instruction that operates on multiple data elements?

SIMD

What type of memory is volatile?

RAM

What is the key characteristic of SISD architecture?

Single instruction operates on single data elements

What is the maximum speedup that can be achieved according to Amdahl's law if 5% of a program is sequential and the remaining part is ideally parallel?

20x

What is the purpose of a pipeline in a CPU?

To increase the instruction execution rate

What type of hazard can be circumvented by register rotation in the Itanium processor?

Data hazard

What is the fastest storage unit in a typical memory hierarchy?

Cache

Which type of architecture is characterized by a single instruction operating on multiple data elements?

SIMD

What is the maximum speedup that can be achieved according to Amdahl's law if 5% of a program is sequential and the remaining part is ideally parallel?

20

Which type of hazard can be circumvented by register rotation in the Itanium processor?

Data hazards

Which type of MIMD systems are best scalable with respect to the number of processors?

Distributed memory computers

For which type of shared (virtual) memory systems is the snooping protocol suited?

Bus based systems

What is the characteristic of SISD architecture?

Single instruction operates on single data element

Which gate is most suitable to make a parity checker?

Exclusive- OR gate

What is the minimum number of flip-flops required in a counter to count 100 pulses?

Seven

What is the advantage of RISC processor over CISC processor?

An instruction can be executed in one cycle

When are interrupts generated?

When memory cycles are stolen

How do devices connected to a microprocessor use the data bus?

Only when sending or receiving data

What is the minimum opcode length required to implement 91 instructions?

7 bits

What type of system is Dynamic RAM best suited for?

Slow systems

What type of CPU architecture is used in Intel Pentium?

RISC-based

Who is commonly considered the inventor of the computer?

Alan Turing

What is the fastest storage unit in a typical memory hierarchy?

Register

Which cache miss does not occur in a fully associative cache?

Conflict miss

What is stored in a Translation Lookaside Buffer (TLB)?

Physical addresses

What is the speedup of a parallel program that achieves an efficiency of 75% on 32 processors?

24

What is the pipelining strategy implemented in?

Instruction prefetch

Which algorithm is a better choice for pipelining?

Merge-Sort Algorithm

What is the concept of pipelining most effective in improving performance if the tasks being performed in different stages?

Require about the same amount of time

Study Notes

Parallel Processing

  • A collection of lines that connects several devices is called a bus.
  • A complete microcomputer system consists of a microprocessor, memory, and peripheral equipment.
  • The PC Program Counter is also called the instruction pointer.
  • A single byte consists of 8 bits.
  • The CPU does not perform data transfer operations.
  • The access time of memory is longer than the time required for performing any single CPU operation.
  • Memory address refers to successive memory words, and the machine is called word addressable.
  • A microprogram written as a string of 0's and 1's is a binary micro-program.
  • A pipeline is like an automobile assembly line.

Processors and Architecture

  • Processors of all computers, whether micro, mini, or mainframe, must have an Arithmetic Logic Unit (ALU), primary storage, a control unit, and can be classified as Single Instruction Single Data (SISD) type.
  • The speedup of parallel programs according to Amdahl's law for an infinite number of processors, if 5% of a program is sequential and the remaining part is ideally parallel, is 20.

Cache and Memory Hierarchy

  • Cache coherence is required for shared (virtual) memory systems and is suited for bus-based systems.
  • The snooping protocol is used for cache coherence in bus-based systems.
  • The fastest storage unit in a usual memory hierarchy is a register.
  • In a system with a 16-bit address bus, the maximum number of 1K byte memory devices it could contain is 256.

Addressing and Memory

  • The most common addressing techniques employed by a CPU are immediate, direct, indirect, and register addressing.
  • The control unit's function in the CPU is to decode program instructions.
  • Memory access in RISC architecture is limited to instructions such as STA and LDA.
  • Interrupts which are initiated by an instruction are external interrupts.
  • Interrupts can be generated from I/O devices.

Input/Output and Peripherals

  • A peripheral is any physical device connected to the computer, such as a tapedrive.
  • CD-ROM is an output device only.
  • Large computer memory is required for applications such as imaging, graphics, and voice.

History and Development

  • The major development that led to the production of microcomputers was the invention of Integrated Circuits.
  • Konrad Zuse is not the correct answer (the correct answer is not provided in the options).

Cache Misses and Pipelining

  • A cache miss that does not occur in case of a fully associative cache is a conflict miss.
  • The cache miss that even occurs in infinite caches is a cold start miss.
  • What is stored in a Translation Lookaside Buffer (TLB) is physical addresses.
  • The concept of pipelining is most effective in improving performance if the tasks being performed in different stages require about the same amount of time.
  • The Merge-Sort Algorithm is a better choice for pipelining.

Parallel Processing

  • A collection of lines that connects several devices is called a bus.
  • A complete microcomputer system consists of a microprocessor, memory, and peripheral equipment.
  • The PC Program Counter is also called the instruction pointer.

Microprocessor

  • A microprocessor is the central processing unit (CPU) of a computer.
  • The CPU does not perform data transfer operations.
  • A microprogram written as a string of 0's and 1's is a binary micro-program.

Memory

  • A single byte consists of 8 bits.
  • The access time of memory is longer than the time required for performing any single CPU operation.
  • Memory address refers to the successive memory words, and the machine is called a word addressable machine.

Pipelining

  • A pipeline is like an automobile assembly line.
  • Data hazards occur when a pipeline changes the order of read/write access to operands.
  • A processor performing fetch or decoding of different instructions during the execution of another instruction is called pipelining.

Parallel Processing

  • Parallel processing may occur in both the instruction stream and the data stream.
  • The cost of parallel processing is primarily determined by Circuit Complexity.
  • Processors of all computers, whether micro, mini, or mainframe, must have a control unit.

Instruction Set Architecture

  • A characteristic of RISC (Reduced Instruction Set Computer) instruction set is one instruction per cycle.
  • A characteristic of CISC (Complex Instruction Set Computer) instruction set is variable format instructions.

Cache and Coherence

  • During the execution of instructions, a copy of the instructions is placed in the Cache.
  • Cache coherence is a problem in shared memory systems, and the snooping protocol is suited for bus-based systems.

Interrupts

  • Interrupts can indicate completion of an I/O operation.
  • Devices connected to a microprocessor can use the data bus only when sending or receiving data.

Other Key Concepts

  • The minimum number of flip-flops required in a counter to count 100 pulses is 7.
  • A parity checker can be made using an Exclusive-OR gate.
  • A RS flip-flop constructed with NAND gates and input R=1 and S=1 has an unused state.
  • The advantage of RISC processors over CISC processors is that an instruction can be executed in one cycle.
  • Dynamic RAMs are best suited for slow systems.
  • Intel Pentium CPU is a RISC-based processor.

Performance and Speedup

  • The speedup of a parallel program that achieves an efficiency of 75% on 32 processors is 24.
  • Pipelining strategy is called implement instruction prefetch.
  • The concept of pipelining is most effective in improving performance if the tasks being performed in different stages require about the same amount of time.
  • Merge-Sort Algorithm is a better choice for pipelining.

Test your knowledge of microcomputer systems, including parallel processing, peripherals, and microprocessors.

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