Memory Hierarchy

Consider a system employing a three-level cache hierarchy (L1, L2, L3) with inclusive properties. If the global miss rate observed at the L3 cache is 5%, and given that the local miss rates for L1 and L2 caches are 40% and 20% respectively, what is the closest approximate global miss rate for the L2 cache?

A cache system uses a 16-way set-associative mapping with a cache size of 64KB and a block size of 64 bytes. If the physical address space is 32 bits, what are the sizes of the tag, set index, and block offset fields, respectively?

Consider a memory system employing a write-back cache policy. Which of the following scenarios would necessitate a write-back operation to main memory?

In the context of cache coherence protocols for multi-processor systems, which of the following describes the purpose of 'snooping'?

Given a DRAM chip organized as 4K x 8 bits, how many such chips are required to construct a 128KB memory?

In the context of memory technology, what distinguishes Spin-Transfer Torque RAM (STT-RAM) from other non-volatile memory types?

Consider a system that uses a virtually addressed cache with a write-through policy. What is the primary challenge that must be addressed to maintain cache coherence in this architecture?

A processor has a two-level cache hierarchy with the following characteristics: L1 cache access time is 1 ns, L2 cache access time is 10 ns, L1 cache hit rate is 95%, and the global hit rate (including both L1 and L2) is 99%. What is the effective memory access time?

In the context of cache design, what is 'cache pollution,' and which strategy is most effective in mitigating it?

Consider a system using ReRAM (Resistive Random-Access Memory). What fundamental physical phenomenon underlies ReRAM's ability to store data?

A memory system uses a two-level page table scheme with a 4KB page size and 4-byte page table entries. If the virtual address space is 48 bits, what is the size of each page table (in bytes)?

In a system with a write-invalidate cache coherence protocol, what is the principal consequence of a processor writing to a shared cache line?

What is the fundamental difference between EPROM and EEPROM concerning how their memory cells are erased?

Consider a processor implementing a non-blocking cache. What architectural feature is essential to prevent the processor from stalling during a cache miss?

Given a fully associative cache with 128 blocks and a block size of 32 bytes, what is the principal advantage of using a Least Recently Used (LRU) replacement policy compared to a First-In-First-Out (FIFO) policy?

In the context of memory address mapping techniques, what is the primary disadvantage of direct mapping compared to set-associative mapping?

Consider a cache system employing a write-back, write-allocate policy. If a cache miss occurs during a write operation, what sequence of actions is initiated?

How does increasing the associativity of a cache typically impact its power consumption, and what is the underlying reason for this change?

Which of the following coherence protocol states typically indicates that a cache line contains the most up-to-date copy of the data and no other cache has a copy of this line?