Memory and I/O Interfacing

• Memory and I/O interfacing are crucial for connecting memories and I/O devices to a microprocessor.

Memories and I/O devices

• These are linked to the microprocessor to facilitate data storage, retrieval, and interaction with the external environment.
• The concept of a stored program, attributed to John von Neumann, means instructions are represented by numbers and stored like data.
• A bit pattern such as 01000101, could represent the number 4516, the letter E as data, or a processor instruction.
• External devices connected to the microprocessor are classified into Memory for storing data & programs, and I/O Devices for external world interaction.

Computer Memory

• Computer memory is a fundamental component used for storing and retrieving data and instructions.
• It acts as an intermediary between the processor and storage devices, providing efficient information access for processing.
• Memory directly impacts a computer's performance, data access, and system efficiency.
• Key reasons for memory importance: storing data and instructions, enabling fast processing, facilitating communication, supporting multitasking and data persistence.
• They store boot and firmware data, and optimizes performance through caching.

Types of Memory

• Computer memory is classified into primary and secondary memory.

Memory Measurement

• Memory and storage are measured using binary multiples.
• 1 Kilobyte (KB) equals 2^10, which equals 1,024 bytes.
• 1 Megabyte (MB) equals 2^20, which equals 1,048,576 bytes.
• 1 Gigabyte (GB) equals 2^30, which equals 1,073,741,824 bytes.
• 1 Terabyte (TB) equals 2^40, which equals 1,099,511,627,776 bytes.
• 1 Petabyte (PB) equals 2^50 bytes.

Memory Organization

• Memory is divided into small parts called cells, each with a unique address ranging from 0 to (Memory Size - 1).
• A computer with 64K words has 64 × 1024 = 65,536 memory locations addressed from 0 to 65535.

Memory Access

• Memory is accessed through read and write operations.
• Read operation fetches data from memory to the processor.
• Write operation stores data from the processor into memory.

Memory Interface design considerations

• Connecting memory chips to a microprocessor requires an interface circuit that matches memory requirements to microprocessor signals and uses an appropriate address decoding strategy.
• The microprocessor interfaces with memory devices using external buses like Control, Address, and Data Bus
• The Address Bus selects memory locations
• The Data Bus transfers data/instructions
• The Control Bus sends control signals for read/write operations

I/O Interfacing

• I/O interfacing facilitates communication between the microprocessor and external devices other than memory.
• Two types of I/O Interfacing: Memory-Mapped I/O and Port-Mapped I/O (Isolated I/O)
• Memory-mapped I/O uses the same address space for both memory and I/O devices, accessing I/O devices like memory locations.
• Port-mapped I/O uses separate address spaces for memory and I/O and uses special I/O instructions (IN, OUT) for communication.

I/O Interface components

• I/O interfaces include input devices like keyboards, mice, and sensors, output devices like displays, printers, and actuators, and ports like parallel and serial ports for data transfer.

Address Decoding

• Address decoding is essential because memory space is not physically homogeneous and is used for different purposes like RAM, ROM, and I/O.
• Address decoding ensures only one memory-mapped component is accessed for a given address, since multiple ICs are used to implement the memory space.
• Address bus lines are divided into MSB for generating chip select signals and LSB for internal addresses within the memory chip.

Address Decoding, simple example

• A microprocessor with 10 address lines (1KB memory) implementing memory space using 128x8 memory chips, needing 8 chips total.
• 3 address lines select each of the 8 chips (2^x lines = 8).
• Each chip needs 7 address lines to address its internal memory cells (2^y lines = 128).

Types of Address Decoding

• All addressable memory space may not need to be implemented, so there are two basic strategies to generate chip select signals.
• They are Full Address Decoding and Partial Address Decoding
• Full Address Decoding uses all address lines for unique device selection, ensuring no two devices share the same address.
• Address lines A9-A0 uniquely identify each device.

Full Address Decoding

• Considering a microprocessor with 10 address lines (1KB memory) and only implementing 512 bytes of memory, half of its capacity.
• The implementation of 512 bytes is done by 128x8 memory chips, needing 4 chips total (512/128 = 4 chips)
• 2 address lines are needed to select each of the 4 chips (2^z lines = 4).
• Each chip needs 7 address lines to address its internal memory cells (2^y lines = 128).
• With 9 lines used, all 10 lines must be used for addressing in full address decoding, and physical memory resides in the upper half of the memory map.
• MSB lines, if unused, are filled with 0’s.

Partial Address Decoding

• Partial Address Decoding uses fewer address lines for device selection and some address lines are left as "don’t cares", allowing multiple addresses for a device.
• This method can lead to aliasing, where multiple addresses map to the same device.

Partial Address Decoding Example

• A microprocessor with 10 address lines (1KB memory) only implementing 512 bytes of memory.
• Memory is implemented using 128x8 memory chips (4 chips total).
• 2 address lines would be used to select each of the 4 chips (2^2 lines = 4).
• Each chip will need 7 address lines to address its internal memory cells (ie. 2^y lines = 128, where y lines = 7 lines).
• With 9 lines are used, only the 9 lines must be used for addressing in a partial address decoding strategy.
• Physical memory will be placed on the upper half of the memory map and MSB is not used will be filled with X's.

Memory Address Map

• A memory address map is a pictorial representation of the assigned address space for each chip/device in the system.
• It shows where each device starts and ends, allowing all the maximum addressable space to be implemented.
• Considering there is a 1KB maximum addressable space, and there are four 128B RAM chips and one 512B ROM chip
• Assuming the chips have been placed on the upper end of the memory space starting at address $000000. Then the RAMs come before the ROM.
• The address ranges are a result of the sizes of each of the components, understanding the number systems in place can help arrive at these addresses.