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Questions and Answers
What should be done if a violation is seen near the Macro/pushdown cell corner and voltage area boundaries meet?
Replace the my_ec0zhi0m1pb1n60x5 with my_ec0zhy0m1pb1n60x5 cell.
What is the max allowed space between any Diffcon edges in either direction?
0.412 um
What does the violation my_DC_06 indicate?
It indicates the max allowed spacing between 2 tcn layers is 0.412 um.
How can the violation my_DC_06 be fixed?
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What spacing must be maintained from my_TRHALFTOM1D to the tcn to avoid my_DWS violations?
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In what situations can the method of adding dummy tcn be used to fix violations?
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