Jetson AGX Orin Software Features Quiz

Jetson AGX Orin Software Features

• Bootloader:
  • Uses BPMP processor boot binaries stored in QSPI for cold boot, and downloaded over USB for recovery mode.
  • Uses UEFI for the next stage boot.
  • Supports QSPI storage device and GPT partition tables (with protective MBR).
  • Does not support file systems.
  • Supports I2C bus.
  • Provides a console UART.
  • Cold boot: QSPI, RCM boot: Downloaded over USB recovery port

Toolchain

• Aarch64 toolchain:
  • Uses gcc-9.3-glibc-2.31 for 64-bit kernel and user space.

Kernel

• Linux kernel version: 5.10.87

Camera Interface

• Features: TBD
• Notes: TBD

LSIO

• UART:

  • Supports PIO mode (FIFO access using CPU) and DMA mode (FIFO access using DMA).
  • Includes hardware/software flow control (toggling flow control lines).
  • Supports buffer throttling based on receive buffer data.
  • Allows selection of Rx and Tx DMA modes.
  • Includes interrupt and polling modes for data transfer completion handling.
  • Supports MCR control for modem access.
  • Allows baud rate/port configuration and adjustment.
  • Adjusts baud rate to fall within tolerance range.

• I2C Master:

  • Supports Standard, FM, and FM+ speed modes.
  • Allows repeat start and no start conditions.
  • Includes packet, normal/byte, 7-bit/10-bit addressing modes.
  • Utilizes APB/GPC DMA for FIFO access.
  • Employs clock gating and always-on clock control for power saving.
  • Supports runtime power management.
  • Allows dynamic clock speed changes and interrupt-based/polling transfer completion.
  • Provides bit-banging for data transfer through GPIO APIs.
  • Handles multiple transfer requests and bus clear support.
  • Supports >4K and >64K splits for software-based configurations.
  • Configures bus speed.

• SPI Master:

  • Supports packed/unpacked data formats in FIFO.
  • Offers full-duplex mode for simultaneous read/write.
  • Allows the selection of least significant bit/byte first.
  • Includes dual SPI for MISO/MOSI as Rx/Tx.
  • Has hardware-based CS control (chip select) and manages setup/hold times.
  • Supports software or hardware-based chip select polarity (active high/low).
  • Provides SPI communication support in Modes 0, 1, 2, and 3.
  • Includes DMA and PIO (non-DMA) modes for data transfer to/from FIFO.
  • Enables GPIO-based chip select control.
  • Supports different clock rates.
  • Provides clock delay between packets.

• GPIO:

  • Provides GPIO request/free and access permission.
  • Integrates pinmux with GPIO APIs.
  • Configures GPIO direction and value.
  • Enables interrupt support from all pins.
  • Includes support for wakeup from SC7.
  • Provides GPIO register dump and SYSFS support.
  • Includes support for suspend/resume.
  • Configures pinmux properties (pull-up/down, input, tristate).
  • Supports drive strength configuration.
  • Configures pinmux function.
  • Configures pinmux properties.

• APBDMA/GPCDMA:

  • Enables memory-to-memory transfers.
  • Supports memory-to-I/O and I/O-to-memory transfers.
  • Includes cyclic-once mode and transfer completion through interrupts.
  • Allows multiple transfer requests with a queue mechanism.

• WATCHDOG:

  • Provides watchdog framework support.
  • Detects CPU hangs and triggers system reset.
  • Includes support for suspend/resume and watchdog interrupt handling.
  • Provides polling/ping support for watchdog activity.

• PWM:

  • Supports PWM register operations.
  • Facilitates Tegra-specific controller configurations.
  • Enables clock accuracy calculation.

• PMC:

  • Enables I/O PAD voltage control (PWR_DETECT).
  • Offers I/O Deep Power Down (DPD) configuration.
  • Provides IO_NOPOWER configuration.
  • Includes access to PMC registers.
  • Supports PMC configuration for bootrom I2C and MMIO commands.
  • Controls LED blinking, including in deep sleep.
  • Allows for soft LED breathing control for ramp-up/down and ON time.
  • Enables RPM (Revolutions Per Minute) reading.
  • Configures pad voltage control by software.
  • Configures deep power down.
  • Configures IO_NOPOWER through regulator.

• BPMP I2C Master:

  • Supports configuration in Standard, FM, and FM+ modes, packet mode, normal/byte mode, 7-bit/10-bit addressing.
  • Includes DMA-based FIFO access.
  • Includes bus clear support when a device holds the bus.

• SPE-UART:

  • Supports PIO mode and DMA mode for FIFO access.
  • Provides hardware flow control.
  • Includes FIFO mode for UART control.
  • Enables SPE DMA and memory-to-memory, memory-to-I/O, and I/O-to-memory transfers.
  • Supports cyclic mode.

• I2C SLAVE:

  • Supports normal/byte mode, FIFO mode, 7-bit and 10-bit addressing.
  • Allows repeat start and clock stretching.

• CAN 2.0 A: -(Supports CAN FD for increased data throughput (~3.7 Mbps). Handles 10 Mbps over 10 meters and 15 Mbps max signal frequency). -Supports standard and extended frame CAN messages at various bit rates. -Includes Tx+Rx standard frame and extended frame modes, with various bit rates. -CAN Loopback support. -Supports Standard and Extended frame with bit rate switching and non-bit rate switching. -Provides timestamping of Tx/Rx frames. -Supports listen-only mode. -Supports restarting the bus after bus-off.

• QSPI:

  • Offers support for single, dual, and quad interface widths.
  • Provides SDR and DDR modes with supported bit lengths (8, 16, and 32).
  • Includes transfer modes 0 and 3.
  • Supports DMA/PIO mode selection and packed/unpacked data formats in FIFO.
  • Manages endianness (least significant bit/byte first).
  • Implements hardware-based CS control with setup/hold times and configurable chip select polarity (SW/HW).
  • Enables combined sequence mode transfer with support for different clock rates and golden register settings for platform configurations.

• HSIO:

  • Ethernet support for speed mode changes.

• (Supports 10/100 Mbps, 1000 Mbps, and 10000 Mbps speeds).

  • Offers half-duplex support.
  • Includes functions for ARP offload, IEEE 1588-2008 (PTP), Energy Efficient Ethernet, checksum offloading (transmit and receive).
  • Supports jumbo frames (up to 9 KB).
  • Includes flow control /PAUSE frame and EAVB support.
  • Features up to 4 TX/RX queues with 4 KB capacity and VLAN insertion/stripping.
  • Includes ethernet ping, remote wakeup and NFS boot.
  • Has Support for speed modes via ethtool.

• PCIe:

  • Supports various link widths (x1, x2, x4, x8) with relevant maximum widths.
  • Includes legacy interrupts, MSI & MSI-X interrupts.
  • Includes maximum payload sizes of 128 bytes and 256 bytes.
  • Supports various PCIe generations (Gen 1-4).
  • Provides Advanced State Power Management (ASPM) levels L0s, L1, L1.1, and L1.2.
  • Supports wakeup and AER (Advanced Error Reporting).
  • Includes DMA support in root ports.
  • Provides endpoint support.

• SDMMC:

  • Supports DR50, HS200, HS400, and HS533 modes.
  • Includes support and tuning for SDMMC controllers.
  • Enables packed command transfers for efficiency.
  • Provides functions such as data cacheing, discarding data, and sanitizing data.
  • Supports packed command (read/write) transfers.

• RPMB:

  • Provides secure access.

• BKOPS:

  • Allows background operations while the host is unavailable.

• HPI:

  • Provides high-priority interrupts for stopping BKOPS/reliable writes.

• Power-Off Notification:

  • Prepares the device for a proper power-off

• Sleep:

  • Enables power minimization.

• RTPM:

  • Enables power saving by switching off clocks during inactivity.

• Field Firmware Upgrade:

  • Enables eMMC firmware updates.

• Device Life Estimation:

  • Provides NAND flash program/erase cycle information as a percentage of the flash's total lifetime (Type A for SLC devices, Type B for MLC devices).

• PRE EOL Information:

  • Provides indication about device lifetime reflected by average reserved blocks.

• Hardware Command Queue:

  • Implemented by the SD/MMC controller.

• Enhanced Strobe Mode (ESM) in HS400 mode:

  • Optional, enabled by the EXT_CSD register.

• eMMC CQ CQIC feature:

  • Produces coalesced interrupts for enabled interrupt coalescing mechanism.

• UFS:

  • Supports PWM-Gx (low performance) and HS-Gx (high performance) modes.
  • Enables native command queue support.

• Hibernation:

  • Provides low power state.

• PWM modes:

  • Supports slow and auto modes for PWM

• HS FAST modes:

  • Offers high-performance configurations for UFS.
  • Includes different HS rate series (A, B).

• USB 3.0:

  • Supports Super Speed Plus Host (10 Gbps), Super Speed (5 Gbps), High Speed (480 Mbps), Full Speed (12 Mbps), and Low Speed (1.5 Mbps) modes.
  • Enables support for auto suspend, remote wakeup, and auto resume for USB host.

• ELPG (Engine Level Power Gating):

  • Supports power gating for xUSB HS and SS partitions.

• Lower Power State:

  • U3 state support

• LPM States:

  • U1 and U2 states support.
  • Hot Plug support
  • Port Multiplier Support

• Host Mass storage, Host USB video class and Host USB ECM: Supporting various USB communication protocols, including mass storage, video, and ECM.

• Host USB audio class, Host USB Modem–NCM, USB HID protocols, Super Speed Device (xUSB) and High Speed Device (xUSB):

• BC1.2 charging, Apple charger detection, MTP, ADB, RNDIS: Supporting battery charging, Apple charger detection, and various data transfer protocols.

• OTG:

  • Supports USB host and device interactions.

• DisplayPort:

  • Supports EDID, DP hot-plug, DP 4K @60 Hz, DP 4K @120 Hz or 8K @30 Hz (HBR3 support).
  • Supports seamless display, enhanced framing, and full link training.
  • Includes error recovery and signaling.
  • Employs HPD_IRQ events for link synchronization feedback.
  • Enables driver suspend/resume and primary/dual display support.
  • Supports link rates (1.62, 2.7, 5.4 Gbps (up to HBR2) and 8.1 Gbps (HBR3 beta)).
  • Provides support for DP Alt Mode / Type-C and DP aux link.
  • Enables sideband information transmission.

• Security Engine:

  • Features are TBD.

• Power Modes:

  • Provides 10W, 15W, and 30W profiles.
  • Includes an NVPModel interface for custom mode creation.

• RTC:

  • Provides alarm functionality and wakeup from SC7.

• System:

  • Supports rebooting and shutdown.
  • Includes SC7 related functions, CPUidle mechanisms, support for waking up from idle/sleep, CPU hotplug.
  • Enables DVFS (Dynamic Voltage and Frequency Scaling) control CPU/GPU frequencies.
  • Allows EMC bandwidth management for controlling power usage.
  • Provides power monitor, clock, and thermal management.
  • Provides support for initrd boot.
  • Supported booting with ATF (Arm Trusted Firmware) as secure monitor.
  • Includes support for experimental generic timestamping on LIC IRQ lines and AON GPIOs.