Interrupt Handling: 8259A PIC

Multiple Peripheral Interrupts

• Most computers have multiple peripherals, but the processor has a single INTR signal.
• ORing interrupt signals from peripherals can solve a single-issue but the problem is with the interrupt type, specifically the IRQ number, during the interrupt ACK cycle.
• If multiple peripherals drive the data bus with the IRQ number at the same time this can be disastrous.
• The IRQ number for peripherals should be somewhat dynamic.
• There should be a provision to decide IRQ numbers at hardware/software system design time, or run-time.
• A smart bridge should sit between the processor and peripherals, concatenating the interrupts and handling the IRQ.
• Programmable Interrupt Controllers (PICs) implement this as standard.
• The Intel 8259 PIC was popular on 8086-based systems.

8259A PIC

• The processor views the 8259 as an I/O peripheral.
• It comes in a 28-bit DIP or PLCC package with a 5V supply
• An 8259 requires no separate clock for operation.
• it can accept 8 interrupts natively.
• Through cascading, it supports up to 64 interrupts to the processor.
• It supports both edge and level triggered interrupts.
• The 8259 supports fixed and rotating priority.
• CS' (Chip Select), -WR' (Write), and -RD' (Read) are the control signals for chip selection
• RD' and WR'.
• An 8-bit data bus connects to the processor data bus.
• The Interrupt (INT) pin connects to the Interrupt Request pin of the processor.
• -INTA' ('Interrupt Acknowledge') connect to the INTA pin of the processor.
• One address pin connects to the processor address bus, usually A1 for 8086.
• Eight interrupt signals from peripherals connect to IR0-IR7

Basic Sequence of Operation (with 8086)

• One or more INTERRUPT REQUEST lines (IR7-0) are raised high, setting the corresponding IRR bit(s).
• The 8259 evaluates the requests and sends an INT to the CPU, if appropriate.
• The CPU acknowledges the INT and responds with an INTA pulse.
• Upon receiving an INTA from the CPU, the highest priority ISR bit is set, and the corresponding IRR bit is reset.
• 8086 initiates a second INTA pulse during which the 8259A releases an 8-bit pointer onto the Data Bus; the CPU reads this, completing the interrupt cycle.
• The ISR bit may reset at the end of the second INTA pulse, depending on the mode of operation.

Programming 8259A

• 8259 needs configuration from the processor via software for operation using command words that get latched inside the 8259.
• The command words come over the data bus from the processor. WR' and CS' signals should be active.
• There are two types of command words: Initialization Command Words (ICWs) and Operation Command Words (OCWs).

Initialization Command Words (ICWs)

• Before normal operation, each 8259A must be brought to a starting point using a sequence of 2 to 4 bytes.
• Commands are written in a predefined sequence. With a single address line, the 8259 can store multiple command words in internal registers.
• When a command is issued with A0 = 0 and D4 = 1, it will be interpreted as Initialization Command Word 1 (ICW1).
• Initialization is usually only done once, but the 8259 can be re-initialized any time by reissuing an ICW1.
• ICW1 configures settings such as whether ICW4 is needed, the trigger mode and if a single or cascade mode is needed
• ICW2 is used to specify the interrupt type (IRQ number)
• ICW3 is applicable only in cascaded mode and states whether in a cascade mode or not, configured by ICW1
• ICW4 is only applicable if the IC4 bit is set in ICW1 and should always be present for 8086

Operation Command Words (OCWs)

• After programming the Initialization Command Words (ICWs) into the 8259A, it is ready for interrupt requests
• During 8259A operation, algorithms can command the 8259A to operate in various modes through the use of Operational Command Words (OCWs).
• there are 3 OCWs.

OCW1

• OCW1 sets and clears the mask bits in the Interrupt Mask Register (IMR), where M7 to M0 represent the eight mask bits.
• M = 1 indicates the channel is masked or inhibited, while M = 0 indicates the channel is enabled.

Fully Nested Mode of Operation

• This is the default 8259 operating mode and enters this mode automatically after initialization.
• Interrupt requests are ordered in priority from 0 through 7, with 0 being the highest priority.
• When one or more Interrupt Request (IR) signals go high, corresponding bits in the Interrupt Request Register (IRR) become high.
• The priority resolver checks for any unmasked interrupt bit in IRR. If bits are set whose priority level is higher than the currently serviced interrupt, the INTR signal to the processor goes high.
• During the first INTA', the state of IRR is frozen. The priority resolver chooses the highest unmasked interrupt and makes the corresponding ISR bit high.
• When the processor issues the second INTA', the IRQ number (type) corresponding to the SET ISR is placed on the data bus.
• This completes the interrupt cycle.

End of Interrupt

• An end of interrupt is detected when a corresponding bit in the In-Service Register (ISR) is cleared.
• How the 8259 detects an end of interrupt depends on the Automatic End Of Interrupt (AEOI) bit setting in ICW4.
• If the AEOI bit is set, the rising edge of the second INTA' signal is treated as the end of the interrupt, and the ISR bit is cleared.
• If 8259 is configured in fully nested mode with AEOI, no more than one bit will be set in the ISR at any given time.
• If the AEOI bit is not set, 8086 must write a command to 8259 to indicate the end of an interrupt.
• The command can be issued using an OCW2.
• When a non-specific EOI command is issued, the ISR bit corresponding to the highest priority interrupt is cleared.
• Alternatively, the processor can use a specific EOI in order to specify the interrupt to clear.

Automatic Rotation Mode

• In some applications, there are multiple interrupting devices of equal priority.
• In this mode, a device, after being serviced, receives the lowest priority.
• A device requesting an interrupt will have to wait, in the worst case, until each of 7 other devices is serviced at most once.
• This mode is also set using OCW2
• Using 'Rotate on non-specific EOI' command in OCW2 rotates priorities.

Special Mask Mode

• An 8259 automatically masks interrupts whose priority is lower than the currently serviced interrupt except in certain applications where low priority interrupts may need detecting.
• In special Mask Mode, when a mask bit is set in OCW1, it inhibits further interrupts at that level and enables interrupts from all other levels (lower as well as higher) that are not masked.
• This means that only interrupts which are explicitly masked in the IMR' are inhibited, and all other interrupts will be propagated to the processor.
• Special Mask Mode is set with the help of OCW3.

Polling Mode

• In this mode, the processor does not use the INT signal from 8259 to detect an interrupt, but polls 8259 directly.
• In order to do this, an OCW3 is first written with the P bit set.
• The next read after this write (RD' low CS' low) will return a pending interrupt, if one exists.
• The IS Register is internally frozen by the poll command (OCW3 write) and status reading.
• Also, the read operation is treated as interrupt acknowledge, and the corresponding bit in the ISR is set.
• The INT signal from 8259 will still be asserted when there is an interrupt, but it may either be disconnected to the processor or masked by clearing Interrupt flag (IF).
• The ISR bit is cleared using the End of Interrupt (Eol) command.
• Polling command contains information such as whether there is a pending interrupt and a binary code of the pending interrupt with highest priority.

Reading 8259 Registers

• In addition to interrupt status, other registers from 8259 can be read when in polling mode.
• If OCW3 is used to configure reading the IRR, any subsequent read operations with A0 bit set to 0 will return the IRR status.
• There is no need to write OCW3 before each IRR read.
• 8259 remembers the last read setting.