Instruction Fetch and Execute

Instruction Fetch and Execute

• Contemporary computer designs are based on concepts developed by John von Neumann
• The von Neumann architecture stores data and instructions in a single read-write memory
• Contents of memory are addressable by location, regardless of data type
• Execution occurs sequentially unless modified

Hardwired Program

• Data flows into a sequence of arithmetic and logic functions, producing results, illustrating a direct path from input to output

Program Concept

• Instruction codes are processed by an instruction interpreter, which generates control signals.
• These signals direct general-purpose arithmetic and logic functions using input data to generate results

Control Unit – Instruction Decoder

• Each operation is assigned a unique code (e.g., ADD, MOVE)
• A hardware segment accepts the code and issues control signals

Components

• The Control Unit and Arithmetic and Logic Unit form the CPU
• Data and instructions enter the system (Input) and results exit (Output)
• Temporary storage for code and results is in main memory

Instruction Cycle

• The processor fetches instructions from memory at the beginning of each cycle
• Program counter (PC) holds the address of the next instruction to be fetched
• The PC increments after each instruction unless specified otherwise
• The fetched instruction is loaded into the instruction register (IR)

Instruction Cycle

• Fetch: Retrieves instruction from memory.
• Execute: Performs the action specified by the instruction
• Instructions contain bits that specify the action for the processor
• Actions can be categorized as processor-memory, processor-I/O, data processing, or control

Program Execution Example

• Program counter (PC) stores the address of the current instruction
• Instruction register (IR) contains the instruction being executed
• The accumulator (AC) provides temporary storage

Interrupts

• Mechanism that modules like I/O use to interrupt normal processing

I/O Module

• Ports are similar to registers but connected to physical devices
• Changing the value in a port sends a message to a peripheral device

Interrupt Types

• Can be triggered by a program, timer, I/O, or hardware failure

Interrupt Handling

• The processor and operating system suspend the current program and resume it later from the same point.
• The processor checks for interrupts, indicated by an interrupt signal
• If no interrupt is present, the next instruction is fetched
• If an interrupt is pending, the current program is suspended, its context is saved, the PC is set to the interrupt handler's address, the interrupt is processed, and the context is restored to continue the interrupted program

Multiple Interrupts

• Interrupts can be sequential
• Interrupts can be nested

Bus Interconnections

• Three basic types of computer components or modules needed: the CPU, memory, and I/O
• Paths are required for connecting the modules
• The collection of paths connecting the modules is the interconnection structure

Buses

• Communication pathway connecting two or more devices
• A bus consists of lines, each capable of transmitting binary signals
• A key characteristic of a bus is its shared transmission medium
• Only one device can successfully transmit at a time

System Bus

• Connects major computer components (processor, memory, I/O)
• Consists of 50 to hundreds of separate lines, each with a specific function
• Lines are classified into Data, Address, and Control lines, plus power distribution lines

Address Bus

• Identifies the source or destination of data
• CPU uses it to read instructions from memory
• Bus width determines maximum memory capacity
• The 8080 has a 16-bit address bus, providing 64k address space
• Address lines address I/O ports
• Addresses starting with "01111111" may reference a memory module (module 0) while addresses starting with "10000000" and above refer to an I/O module (module 1)

Control Bus

• Control lines manage access to and use of the data and address lines
• A means of controlling shared data and address lines is needed
• Control signals transmit command and timing information to system modules, encompassing Memory read/write signals, Interrupt requests, and Clock signals

Multiple-Bus Hierarchies

• Modern systems have major components on the same board, integrating more elements on the processor chip
• On-chip bus connects the processor and cache memory
• An on-board bus connects the processor to main memory and other components

Single-Bus Problems

• Propagation delays increase with more devices attached to the bus affecting co-ordination

Bus Types

• Dedicated bus lines are permanently assigned to a function or physical subset of computer components
• Multiplexed buses share lines using time multiplexing and control lines
• Multiplexing reduces the number of lines but increases complexity

Bus Arbitration

• Multiple modules may need control of the bus
• Bus arbitration ensures only one unit transmits at a time
• Centralized schemes use a bus controller or arbiter
• Distributed schemes use access control logic in each module to share the bus

Timing

• Co-ordination of events on the bus
• Synchronous buses uses clock signals for co-ordination and include a clock line
• Asynchronous buses coordinate events without a central clock signal