Field Effect Transistors (FETs)

Field Effect Transistors (FETs)

• FETs utilize an electric field to manage the electrical behavior of a device.
• Known as unipolar transistors, they involve single-carrier-type operation.
• FETs exhibit high input impedance at low frequencies.
• Conductivity between the drain and source is managed by an electric field.
• The electric field is generated by the voltage difference between the body and the gate of the device.

Junction FET (JFET) Operation

• JFETs are a type of FET that use a reverse-biased PN junction to control current in a channel.
• JFETs are categorized as either N channel or P channel, depending on their structure.
• Wire leads connect to each end of the channel.
• The drain is at the upper end, and the source is at the lower end of the channel.
• Two P-type regions diffuse in the N-type material, forming a channel in N-channel MOSFETs.
• Both P-type regions connect to the gate lead.

JFET Circuit and Operation

• DC bias voltages are applied to an N-channel device.
• VDD provides drain-to-source voltage, supplying current from drain to source.
• VGG sets the reverse-bias voltage between the gate and source.
• JFETs operate with the gate-source PN junction reverse biased.
• Reverse biasing the gate-source junction with negative gate voltage creates a depletion region along the PN junction.
• This extends into the N channel, increasing resistance by restricting the channel width.
• Adjusting the gate voltage controlled channel width and resistance.
• Varying the gate voltage controls the amount of drain current, ID.
• White areas in diagrams represent depletion regions.

JFET Characteristics and Voltage

• For conduction, JFETs require biasing.
• Increasing VGG narrows the channel (depletion region), increasing resistance and decreasing ID.
• Channel width varies due to a higher reverse-bias voltage, and it is wider at the drain end.

JFET Characteristics

• This can be observed when the gate-to-source voltage is zero (VGS = 0V).
• Shorting the gate to the source grounds both in a JFET circuit and characteristic curve.
• As VDD (and thus VDS) rises from 0 V, ID increases proportionally.
• Channel resistance is roughly constant in the ohmic area.
• In this area, the depletion region has minimal impact.

Pinch-Off Voltage

• When VGS = 0 V, the VDS value where ID becomes constant (point B on the curve) is the pinch-off voltage (Vp).
• For a JFET, Vp is constant.
• As VDS continues increasing above pinch-off, drain current remains almost constant.
• IDSS (drain-to-source current with gate shorted) is specified on JFET data sheets.
• This is the maximum drain current a JFET can produce.

JFET Operation

• Breakdown occurs at point C when ID rapidly increases with VDS.
• Because breakdown can damage the device, JFETs operate below breakdown within the constant-current area.
• This is between points B and C on the graph.

JFET Characteristic Curve Family

• Applying a bias voltage, VGG, from gate to source creates drain-characteristic curves.
• Increasing the magnitude of VGS causes a decrease in ID.
• This is because the channel narrows.
• For VGS increases, the JFET reaches pinch-off at VDS values below Vp.
• The amount of drain current is controlled VGS.

JFET Cut-Off Voltage

• The cutoff voltage, VGS(off), is the VGS value where ID is zero.
• JFETs must operate between VGS = 0 V and VGS(off).
• The value of ID ranges from a maximum of IDss to a minimum of almost zero.
• For an N-channel JFET, more negative VGS values result in smaller ID values.
• VGS causes ID to reduce to zero because the depletion region widens, fully closing the channel.

P-Channel JFET Operation

• A P-channel JFET's basic operation mirrors that of an N-channel device.
• A P-channel JFET requires a negative VDD and a positive VGS.

Comparison of JFET Pinch-off and Cut-off

• Pinch-off and cut-off are distinct but connected.
• Vp identifies the VDS value where drain current becomes constant, measured at VGS = 0 V.
• Pinch-off occurs at VDS values below Vp when VGS is nonzero.
• Vp is constant, but the minimum VDS value at which ID becomes constant varies with VGS.
• VGS(off) and Vp values are equal in magnitude but opposite in sign.

JFET Self-Bias

• Self-bias is the most common type of JFET bias.
• JFETs must operate with the gate-source junction reverse biased.
• N-channel JFETs need negative VGs, while P-channel JFETs require positive VGs.
• This is achieved through self-bias arrangements.
• The gate resistor, RG, does not affect the bias because it has essentially no voltage drop.

JFET Voltage Divider Bias

• In an N-channel JFET with voltage-divider bias, the source voltage must be more positive than the gate.
• This keeps the gate-source junction reverse biased.

MOSFETs

• The metal-oxide-semiconductor field-effect transistor, or MOSFET, is the second type of field-effect transistor.
• The MOSFET differs from the JFET in that it lacks a PN junction; the gate insulates the channel using silicon dioxide (SiO2).
• The basic types of MOSFETs include depletion (D) and enhancement (E).
• They are known as insulated-gate FETs (IGFETs) due to the gate's insulation.

Depletion MOSFET (D-MOSFET)

• One type of MOSFET is the depletion MOSFET (D-MOSFET).
• The drain and source diffuse into the substrate and connect via a channel adjacent to the insulated gate.
• P-channel and N-channel devices exist. The P-channel operation mirrors the N-channel but with opposite voltage polarities.
• D-MOSFETs operate in either depletion or enhancement modes, sometimes called depletion/enhancement MOSFETs.

MOSFET Voltages

• Due to the gate being insulated, either a positive or negative gate voltage can be applied.
• N-channel MOSFETs operate in depletion mode with negative gate-to-source voltages.
• N-channel MOSFETs operate in enhancement mode with positive gate-to-source voltages.
• These devices typically operate in depletion mode.

Depletion Mode MOSFET

• Visualize the gate and channel as parallel-plate capacitor plates with a silicon dioxide dielectric.
• A negative gate voltage repels conduction electrons, leaving positive ions and depleting the N channel.
• Higher negative gate voltage results in increased N-channel electron depletion.
• At VGS(off), the channel is fully depleted, and drain current is zero.
• Like the N-channel JFET, the N-channel D-MOSFET conducts drain current between VGS(off) and zero.

Enhancement Mode

• A positive gate voltage attracts more conduction electrons into the channel, enhancing conductivity.

D-MOSFET Symbols

• Schematic symbols shown for N-channel and P-channel depletion MOSFETs.
• The substrate may connect internally to the source, indicated by an arrow.
• Inward-pointing substrate arrow denotes N channel; outward points to P channel.

Enhancement MOSFET

• Enhancement MOSFETs (E-MOSFET) operate in enhancement mode only, lacking depletion mode.
• E-MOSFETs differ from D-MOSFETs by lacking a structural channel.
• A positive gate voltage above a threshold induces a channel by creating negative charges.
• The area is in the substrate region adjacent to the SiO2 layer.
• Channel conductivity enhances by raising gate-source voltage and pulling more electrons into a area.
• Channel does not exits below gate threshold voltage.

FET Symbols

• Schematic symbols for both N-channel and P-channel JFETs are shown in the FET symbols image.
• The arrow on the gate points in for the N channel and out for the P channel.