10 Questions
What limits the current through a TFET device?
Rate of BTBT generation
What is more important than gate length in scaling TFETs?
Gate dielectric
How does the ON-current change with gate length reduction in a planar TFET?
Increases logarithmically
What happens to the ON-current when the gate dielectric thickness is reduced?
Increases exponentially
In a TFET, what modulates the lateral electric field at the tunneling junction?
Both gate and source/drain voltages
What is fundamental to all lateral BTBT devices?
Exponential Id vs. Vd curve
What determines the manner in which a device charges/discharges a capacitive load?
Shape of the drain voltage characteristic
Which type of devices show a normalized Id vs. Vd behavior in Fig. 4?
Simulated MOSFET and TFET
What is the key feature in Ge channel TFETs?
Cross-sectional tunneling area increase
What kind of device structure changes are important for TFET improvement?
Changes that enhance control of tunneling
This quiz covers the use of thinner gate dielectrics in epitaxially depositing in-situ doped layers on SOI substrates to improve performance of dTFET structures. It also includes information on channel doping levels and performance comparisons with conventional TFETs.
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