Digital Electronics EE-29(GDE) Grand Test-1

• Grand Test-1 on Digital Electronics review, test code EE -29(GDE).
• The test contains one and two mark questions.
• There is a negative marking of 0.33 for one-mark questions and 0.66 for two-mark questions.

One Mark Questions

• For a 6-bit 1's complement number 100000, the decimal value is A; for a 6-bit 2's complement number 100000, the decimal value is B; A - B = 1.
• The output of a specific logic circuit is A after every odd-numbered gate and 1 after every even-numbered gate.
• 4 is the minimum number of 2 input NAND gates required to implement a 2 input NOR gate.
• The Boolean function F(X, Y, Z) implemented using a decoder and logic gate equals ∏M(1, 4, 5, 7).
• Given two 4-bit binary numbers A and B, there are 120 combinations for which A > B.
• The minimum number of clock pulses to be applied to a 4-bit SIPO right shift register with initial contents Q3 Q2 Q1 Q0 = 0110 to get Q3 Q2 Q1 Q0 = 1111 is 6.
• For a circuit with clock frequency 'f' Hz, the frequency of the output Q is f/2.
• For a given circuit, with each state designated as Q1 Q0, the state transition sequence with an initial state of 00 is 00 -> 01 -> 10.
• For an 8 bit DAC with a reference voltage VR = 10 V, the analog output voltage for the digital input 1000 0110 is 5.226 V.
• Instructions that do not affect the carry flag are INR and DCR.

Two Mark Questions

• The base of the number system for which the relation √144 = 12 is satisfied for any base ≥ 5.
• The simplified Boolean expression for the given K-map is A ⊕ B ⊕ C.
• If F₁= a ⊕ b and F2 = a + b, then the output of the logic gates is a ⊕ b.
• Given the Boolean function F(a, b, c, d) = ∑m(5, 7, 9, 11, 13, 15), for a = 0, d = 1, the function can be expressed as b.
• A 4-bit parallel binary adder implemented using only half adders and OR gates requires a minimum of 3 OR gates.
• A 4x1 Mux implements a 3 input Boolean function F(A, B, C) = ∑m(0, 2, 4, 5).
• With logic gates having a propagation delay of 25 ns and a specific waveform applied at input X, output Y = 0 for a total duration of 50 ns.
• The inputs l0, l1, l2, and l3 for a 4x1 MUX implementing a 3-input EX-OR gate are C, C, C, C.
• The circuit functions as a T flip-flop.
• A JK flip-flop with a propagation delay of 12 ns allows constructing a ripple counter with a largest modulus of 64 while operating up to 12 MHz.
• The characteristic equation of an AB flip-flop, determined from its truth table, is Qn+1 = AQ' + B'Q.
• Input X should be QoQ1 to complete the partial implementation of a 3-bit modulus 8 up-counter.
• The frequency at the output of a cascaded circuit is 125 Hz.
• A read/write memory with a 2K bytes capacity has an address range of F000H to F7FFH or F800H to FFFFH.
• After the execution of a given 8085 program, the contents of the HL pair will be 3002H.
• The instruction "DCR C" gets executed 65279 times in a given code.
• In the DAC circuit with VR = 5V and R = 8kΩ, the voltage Vo is -1.953 volt.
• A dual-slope ADC type DVM will indicate 123.4 mV.
• The output Y in a circuit is always "1" when two or more of the inputs P, Q, R are "1".
• Serial data applied to the Data terminal in nine clock cycles produce a value of Q2Q1Q0 of 010.