DDR SDRAM Technology Evolution

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Questions and Answers

What is the primary innovation of DDR SDRAM?

  • Transferring data on the rising edge of the clock signal
  • Transferring data on the falling edge of the clock signal
  • Transferring data only when the clock signal is steady
  • Transferring data on both rising and falling edges of the clock signal (correct)

What is the voltage reduction from DDR2 to DDR3?

  • From 1.8 to 1.5 V (correct)
  • From 1.2 to 1 V
  • From 1.5 to 1.2 V
  • From 2.5 to 1.8 V

What is the maximum expected clock rate of DDR4?

  • 1333 MHz
  • 1600 MHz (correct)
  • 1000 MHz
  • 800 MHz

How are memories usually sold?

<p>In small boards (DIMM) (A)</p> Signup and view all the answers

What is the function of the activate command (ACT) in DRAM operation?

<p>Opens a bank and row (C)</p> Signup and view all the answers

How is the address multiplexing managed in DRAM operation?

<p>By the DRAM controller (C)</p> Signup and view all the answers

What is the organization of modern DRAM?

<p>In banks and rows (B)</p> Signup and view all the answers

What is the purpose of the precharge command (PRE) in DRAM operation?

<p>Closes a bank and row and prepares it for a new access (D)</p> Signup and view all the answers

What is the purpose of memory interleaving?

<p>To facilitate the handling of memory modules (A)</p> Signup and view all the answers

What is the primary function of virtual memory?

<p>To automatically manage the two levels in the memory hierarchy (D)</p> Signup and view all the answers

What is the bus width of a typical DDR memory module?

<p>64-bit (D)</p> Signup and view all the answers

What happens when a row is not open in main memory?

<p>Precharge is required, leading to a longer access time (A)</p> Signup and view all the answers

What is the clock rate of DDR1 memory in MiB per second?

<p>2128 (C)</p> Signup and view all the answers

What is the term used to describe the process of translating virtual addresses to physical addresses?

<p>Memory mapping (C)</p> Signup and view all the answers

What is the benefit of virtual memory in terms of memory space?

<p>It allows for memory space sharing and protection (B)</p> Signup and view all the answers

What is the term used to describe a block of memory in the context of virtual memory?

<p>Page (C)</p> Signup and view all the answers

What is the main priority of SRAM?

<p>Speed and capacity (D)</p> Signup and view all the answers

What is the benefit of using SRAM in cache memory?

<p>Reducing access time (B)</p> Signup and view all the answers

What is the consequence of quadrupling the memory bus?

<p>The cost becomes prohibitive (B)</p> Signup and view all the answers

What is the term for data that needs to be refreshed periodically in DRAM?

<p>Dynamic (D)</p> Signup and view all the answers

What is the main advantage of using SDRAM over traditional DRAM?

<p>Elimination of synchronization overhead (A)</p> Signup and view all the answers

What is the result of using a 256-bit bus without interleaving?

<p>An effective cycle of 2.92 (A)</p> Signup and view all the answers

What is the speedup of using a 256-bit bus without interleaving compared to a memory interleaving configuration of 4 banks?

<p>1.06 (D)</p> Signup and view all the answers

What is the characteristic of EEPROM?

<p>Non-volatile memory that can be electronically erased and reprogrammed (A)</p> Signup and view all the answers

What is the primary reason why the common approximation considers each bit corresponding to a single way in the cache?

<p>To provide a fixed mapping of cache blocks to cache sets (D)</p> Signup and view all the answers

According to Figure 4.7, which cache replacement strategy results in the lowest number of cache misses in a 256 kBytes two-way associative cache?

<p>Random (B)</p> Signup and view all the answers

What is the primary advantage of making reads faster in cache memory?

<p>Enhancing the common case performance (B)</p> Signup and view all the answers

Why is it not possible to apply the strategy of reading blocks from the cache simultaneously with tag comparison to writes?

<p>Because writes require a confirmation of a hit before proceeding (D)</p> Signup and view all the answers

In a fully associative cache, what determines the placement of a block?

<p>A replacing policy (B)</p> Signup and view all the answers

What is the main purpose of a cache replacement policy?

<p>To optimize the use of cache memory (A)</p> Signup and view all the answers

What is the main advantage of a fully associative cache?

<p>Full flexibility in block placement (A)</p> Signup and view all the answers

What happens when all the bits related to a set in the cache are turned ON?

<p>The bits are reset except for the most recently turned ON bit (C)</p> Signup and view all the answers

What is the primary advantage of using a set associative cache?

<p>Improved cache hit rate (B)</p> Signup and view all the answers

In a direct mapped cache, how is the cache block determined for a given block address?

<p>Using the block address modulo the number of blocks in the cache (C)</p> Signup and view all the answers

What is the main disadvantage of a direct mapped cache?

<p>Possible inefficiency due to inflexibility (B)</p> Signup and view all the answers

What is the main characteristic of a cache replacement policy based on the random strategy?

<p>It chooses the block to replace randomly (C)</p> Signup and view all the answers

In a set associative cache, how is the set determined for a given block address?

<p>Using the block address modulo the number of sets in the cache (D)</p> Signup and view all the answers

What is the term used to describe a cache with n blocks in a set?

<p>n-way set associative (C)</p> Signup and view all the answers

What is the main advantage of a set associative cache over a direct mapped cache?

<p>Higher flexibility in block placement (D)</p> Signup and view all the answers

What is the purpose of a replacing policy in a cache?

<p>To decide which block to replace when the cache is full (D)</p> Signup and view all the answers

What is the primary function of the tag in a cache memory?

<p>To mark the block data validity (A)</p> Signup and view all the answers

In a fully associative cache, how many replacement strategies are commonly used?

<p>3 (B)</p> Signup and view all the answers

What is the principle behind the LRU replacement strategy?

<p>If recently used blocks are likely to be used again, a good candidate for disposal is the least recently used block (B)</p> Signup and view all the answers

What is the main drawback of the LRU strategy?

<p>It is complex to keep track of blocks' usage (A)</p> Signup and view all the answers

What is the advantage of using FIFO replacement strategy over LRU?

<p>It is less complex to implement (A)</p> Signup and view all the answers

In a direct mapped cache, how is the block replacement performed?

<p>Only one block frame is checked for a hit, and only that block index can be replaced (D)</p> Signup and view all the answers

What is the main advantage of using a fully associative cache over a direct mapped cache?

<p>It has more replacement strategies (C)</p> Signup and view all the answers

What is the main characteristic of the cache memory?

<p>It is a small, fast memory that stores frequently accessed data (D)</p> Signup and view all the answers

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Study Notes

DDR SDRAM Technology

  • DDR SDRAM transfers data on both rising and falling edges of the clock signal, hence the term "double data rate".
  • DDR technology has evolved with increased clock rates and voltage reduction:
  • From DDR1 to DDR2, voltage reduced from 2.5V to 1.8V, and clock rates increased to 266, 333, and 400 MHz.
  • From DDR2 to DDR3, voltage dropped to 1.5V with a maximum clock speed of 800 MHz.
  • From DDR3 to DDR4, voltage dropped to 1-1.2V with a maximum expected clock rate of 1600 MHz.
  • DDR5 standard was released in 2020.
  • Memories are usually sold in small boards called dual inline memory module (DIMM), containing 4 to 16 DRAM chips, arranged to provide 8-Byte words.

DRAM Organization and Operation

  • Modern DRAM is organized in banks with up to 16 banks in DDR4, each bank having a number of rows.
  • The address multiplexing is managed by the DRAM controller, which sends bank and row numbers, followed by the column address, to access data for reading or writing.
  • The activate command (ACT) opens a bank and a row, loading the entire row into the row buffer.
  • The precharge command (PRE) closes the bank and row, preparing it for a new access.

RAM Construction Technology

  • Read-only memory (ROM) is a non-volatile memory that can be written just once.
  • Electrically erasable programmable read-only memory (EEPROM) can be electronically erased and reprogrammed at slow speed.
  • Static random-access memory (SRAM) prioritizes speed and capacity, with non-multiplexed address lines, and is 8 to 16 times more expensive than DRAM.
  • Dynamic random-access memory (DRAM) prioritizes cost per bit and capacity, with multiplexed address lines, and requires periodic refreshes.

Memory Physical Modules

  • Memory modules are used in the form factor of DIMM, containing 4 to 16 memory chips, to facilitate handling and exploit memory interleaving.

Virtual Memory

  • Virtual memory (VM) automatically manages the two levels in the memory hierarchy, represented by main memory and secondary storage (disk or flash).
  • Virtual memory provides memory space sharing and protection, and memory relocation.
  • Memory mapping, also known as address translation, is a key concept in virtual memory.

Cache Memory Organization

  • A cache block is identified by a tag, which marks the memory address to which the block corresponds, and includes a valid bit to indicate block data validity.
  • Tags are searched in parallel to ensure speed.

Block Replacement

  • In a direct-mapped cache, the hardware decisions are simplified, with only one block frame checked for a hit, and only that block index can be replaced.
  • In fully associative or set associative caches, there are three main replacement strategies: random, least recently used (LRU), and first-in, first-out (FIFO).
  • The random replacement strategy aims to spread allocation uniformly by random selection of candidate blocks.
  • The LRU replacement strategy keeps track of block accesses to reduce the chance of throwing out data that is likely to be needed soon.
  • The FIFO strategy is an approximation of LRU, determining the oldest block rather than the least recently used block.

Block Placement

  • Cache organizations can be fully associative, direct mapped, or set associative.
  • In a fully associative cache, a block can be placed anywhere in the cache.
  • In a direct mapped cache, each block has only one place it can appear in the cache, determined by the block address modulo the number of blocks in the cache.
  • In a set associative cache, a block can be placed in a restricted set in the cache, determined by the block address modulo the number of sets in the cache.

Cache Organization Aspects

  • Fully associative cache: full flexibility, but complexity and implementation cost.
  • Direct mapped cache: simplicity, but possible inefficiency due to inflexibility.
  • Set associative cache: compromises between flexibility and simplicity.

Write Strategy

  • Reads dominate processor cache accesses, with writes approximately 10% of the memory traffic.
  • The write strategy is different from the read strategy, as the changing of a block cannot start until the tag is checked to confirm whether the address is a hit.

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