DDR SDRAM Technology Evolution

DDR SDRAM Technology

• DDR SDRAM transfers data on both rising and falling edges of the clock signal, hence the term "double data rate".
• DDR technology has evolved with increased clock rates and voltage reduction:
• From DDR1 to DDR2, voltage reduced from 2.5V to 1.8V, and clock rates increased to 266, 333, and 400 MHz.
• From DDR2 to DDR3, voltage dropped to 1.5V with a maximum clock speed of 800 MHz.
• From DDR3 to DDR4, voltage dropped to 1-1.2V with a maximum expected clock rate of 1600 MHz.
• DDR5 standard was released in 2020.
• Memories are usually sold in small boards called dual inline memory module (DIMM), containing 4 to 16 DRAM chips, arranged to provide 8-Byte words.

DRAM Organization and Operation

• Modern DRAM is organized in banks with up to 16 banks in DDR4, each bank having a number of rows.
• The address multiplexing is managed by the DRAM controller, which sends bank and row numbers, followed by the column address, to access data for reading or writing.
• The activate command (ACT) opens a bank and a row, loading the entire row into the row buffer.
• The precharge command (PRE) closes the bank and row, preparing it for a new access.

RAM Construction Technology

• Read-only memory (ROM) is a non-volatile memory that can be written just once.
• Electrically erasable programmable read-only memory (EEPROM) can be electronically erased and reprogrammed at slow speed.
• Static random-access memory (SRAM) prioritizes speed and capacity, with non-multiplexed address lines, and is 8 to 16 times more expensive than DRAM.
• Dynamic random-access memory (DRAM) prioritizes cost per bit and capacity, with multiplexed address lines, and requires periodic refreshes.

Memory Physical Modules

• Memory modules are used in the form factor of DIMM, containing 4 to 16 memory chips, to facilitate handling and exploit memory interleaving.

Virtual Memory

• Virtual memory (VM) automatically manages the two levels in the memory hierarchy, represented by main memory and secondary storage (disk or flash).
• Virtual memory provides memory space sharing and protection, and memory relocation.
• Memory mapping, also known as address translation, is a key concept in virtual memory.

Cache Memory Organization

• A cache block is identified by a tag, which marks the memory address to which the block corresponds, and includes a valid bit to indicate block data validity.
• Tags are searched in parallel to ensure speed.

Block Replacement

• In a direct-mapped cache, the hardware decisions are simplified, with only one block frame checked for a hit, and only that block index can be replaced.
• In fully associative or set associative caches, there are three main replacement strategies: random, least recently used (LRU), and first-in, first-out (FIFO).
• The random replacement strategy aims to spread allocation uniformly by random selection of candidate blocks.
• The LRU replacement strategy keeps track of block accesses to reduce the chance of throwing out data that is likely to be needed soon.
• The FIFO strategy is an approximation of LRU, determining the oldest block rather than the least recently used block.

Block Placement

• Cache organizations can be fully associative, direct mapped, or set associative.
• In a fully associative cache, a block can be placed anywhere in the cache.
• In a direct mapped cache, each block has only one place it can appear in the cache, determined by the block address modulo the number of blocks in the cache.
• In a set associative cache, a block can be placed in a restricted set in the cache, determined by the block address modulo the number of sets in the cache.

Cache Organization Aspects

• Fully associative cache: full flexibility, but complexity and implementation cost.
• Direct mapped cache: simplicity, but possible inefficiency due to inflexibility.
• Set associative cache: compromises between flexibility and simplicity.

Write Strategy

• Reads dominate processor cache accesses, with writes approximately 10% of the memory traffic.
• The write strategy is different from the read strategy, as the changing of a block cannot start until the tag is checked to confirm whether the address is a hit.