CS 221 Logic Design: Combinational Circuits

CS 221 Logic Design

• Course code: CS 221
• Year: 2023
• Instructor: Dr. Soha Ahmed Ehssan

Combinational Circuits (Lecture 6)

• This lecture covers standard combinational circuits.
• Key circuits include adders, subtractors, comparators, decoders, encoders, and multiplexers.
• The aim is to understand the design process of such circuits.
• Internal design and functionality of each circuit will be examined.

Decoders

• Decoders are combinational logic building blocks.
• They convert an input binary number into a single high output.
• A 2-input decoder has 4 possible input binary numbers.
• Therefore, it has 4 outputs, one for each input binary number.
• Decoders are also known as n-to-m line decoders, where m ≤ 2ⁿ.
• A practical application for decoders is binary-to-octal conversion.
• Inputs represent the binary values and outputs represent the octal equivalent.

3-to-8 Line Decoder

• A 3-input decoder has 8 outputs (2³).
• The truth table for a 3-to-8 decoder shows the output for all possible input combinations.
• Outputs are labelled D₀ to D₇, which correspond to the minterms of the input variables.
• Example minterm representations: D₀ = x'y'z', D₇ = xyz.

Decoders (Enable Input)

• Decoders can include an enable input (E).
• When E=0, all outputs are 0.
• When E=1, the decoder functions normally.

4-to-16 Line Decoder

• This combines two 3-to-8 line decoders with enable inputs.
• One decoder is active when w=0, the other when w=1.
• The active decoder generates minterms based on its enabled input combination.

Exercise

• The exercise involves designing a 4×16 decoder using 2×4 decoders.

Boolean Function Implementation

• Any Boolean function can be expressed as a sum of minterms.
• A decoder with an external OR gate enables the implementation of any Boolean function.
• Example: Full-adder functions using a decoder.

Encoders

• Encoders perform the reverse operation of decoders.
• They have 2ⁿ inputs and n outputs.
• A common application is octal-to-binary conversion.
• One input can only have a value of 1 at a time.

Octal-to-Binary Encoder

• The truth table outlines the input-output relationships in octal-to-binary conversion.
• The output binary values correspond to the activated octal input.
• This implementation uses multiple OR gates.
• Encoders have limitations when multiple input values are active at once.

Priority Encoder

• A priority encoder addresses the limitations of a standard encoder.
• It prioritizes inputs based on input levels.
• The highest priority input determines the output code.
• The truth table outlines the expected output for various input combinations.

Multiplexers

• Multiplexers (MUXs) select a single input line from many lines.
• They have 2ⁿ data inputs, n selection lines, and a single output line.

Two-to-One Multiplexer

• A 2-to-1 MUX has two data inputs and a single selection input.
• These inputs select which data input is routed to the output.

Four-to-One Multiplexer

• A 4-to-1 MUX has four data inputs and two selection inputs.
• The selection inputs control which data input is passed to the output.

Multiplexer with Enable Input

• Multiplexers can have an enable input.
• When E=0, all outputs are 0.
• When E=1, the normal multiplexer functionality is enabled.

Quadruple 2-to-1 Line Multiplexer

• A 4-input MUX selects one of two 4-bit numbers based on the enable and select inputs.
• The enable input E must be active for normal operation.

Boolean Function Implementation (Cont.)

• Specific examples illustrate implementing Boolean functions using multiplexers.

This quiz explores key aspects of combinational circuits, focusing on decoders and their functionalities. Students will delve into the design, internal structure, and applications of various circuits, including adders, subtractors, and multiplexers. Gain a deeper understanding of how these components operate within logic design.