CPU Registers Explained
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Questions and Answers

Which hardware component is primarily responsible for keeping track of the next instruction to be executed in a program?

  • Program Counter (PC) (correct)
  • Processor Status Register
  • Stack Pointer
  • General Purpose Register

Where are local variables and return addresses typically stored during function calls?

  • Program Counter
  • General Purpose Registers
  • Stack (using Stack Pointer/Frame Pointer) (correct)
  • Processor Status Register

What is the primary function of the Processor Status Register?

  • Storing the address of the next instruction.
  • Managing memory allocation for function calls.
  • Storing condition codes and control flags. (correct)
  • Holding general-purpose data for computations.

When an interrupt occurs, what mechanism is used to find the appropriate interrupt handling routine?

<p>The Interrupt Vector table. (B)</p> Signup and view all the answers

What is the role of general purpose registers in the CPU?

<p>They store temporary data and intermediate results during computations. (D)</p> Signup and view all the answers

Which of the following is NOT directly managed by the stack pointer/frame pointer?

<p>Global variable addresses (B)</p> Signup and view all the answers

A program is executing a loop. Which register is most likely being updated in each iteration to control the loop?

<p>A General Purpose Register (B)</p> Signup and view all the answers

Which of these scenarios would most likely cause a change in the Processor Status Register?

<p>An arithmetic operation results in an overflow. (B)</p> Signup and view all the answers

During the basic instruction cycle, what is the primary role of the Program Counter (PC)?

<p>To hold the memory address of the next instruction to be fetched. (B)</p> Signup and view all the answers

Which of the following actions is typically restricted when a processor is operating in user mode?

<p>Directly accessing I/O devices or specific memory regions. (B)</p> Signup and view all the answers

What is the purpose of an interrupt vector in handling hardware interrupts?

<p>To map interrupt requests to corresponding interrupt service routines. (A)</p> Signup and view all the answers

In a system that uses kernel mode and user mode, which mode has unrestricted access to hardware and memory?

<p>Kernel mode, for managing system resources and handling interrupts. (B)</p> Signup and view all the answers

Consider a scenario where a program is executing in user mode and needs to perform a privileged operation, such as accessing a hardware device. How does the program typically request this operation?

<p>By triggering an interrupt or trap, which switches the processor to kernel mode to handle the request. (B)</p> Signup and view all the answers

In the provided assembly code, what is the virtual address of the store R1, 0xA2 instruction?

<p>0x14 (D)</p> Signup and view all the answers

In the context of memory management and function calls, what is the primary role of the stack pointer?

<p>To manage the allocation and deallocation of memory for function parameters and local variables. (C)</p> Signup and view all the answers

Which register typically contains status information about the most recently executed instruction, such as overflow, carry, or zero flags?

<p>Processor Status Register (PSR) (C)</p> Signup and view all the answers

During a context switch, which of the following program state components is NOT typically saved?

<p>Memory Address Space (A)</p> Signup and view all the answers

What is the primary role of the interrupt vector?

<p>Mapping interrupt requests to specific memory addresses or function pointers (C)</p> Signup and view all the answers

In the context of interrupt handling, what is the purpose of 'masking off' an interrupt?

<p>To temporarily delay or disable the interrupt (B)</p> Signup and view all the answers

Which of the following is the correct sequence of actions taken by the CPU when an interrupt occurs?

<p>Save PC on stack -&gt; Switch to Kernel Mode -&gt; Load PC from vector -&gt; Save all registers -&gt; Continue execution (B)</p> Signup and view all the answers

What is a 'critical section' in the context of concurrent programming?

<p>A piece of data shared between threads that must have mutual exclusive access. (D)</p> Signup and view all the answers

In the provided code snippet, why is the variable c a point of concern in a multi-threaded or interruptible environment?

c = 'A';
for (i = 0; i < MAX; i++) {
    a[i] = c++;
    if (c > 'E')
        c = 'B';
}

<p>Because it's value affects multiple iterations and can be changed unexpectedly. (A)</p> Signup and view all the answers

What potential issue arises if an interrupt service routine (ISR) modifies a variable that is also being used in a main program loop without proper synchronization?

<p>A race condition may occur, leading to data corruption or unexpected behavior. (D)</p> Signup and view all the answers

Which register is crucial for resuming execution at the correct location after handling an interrupt?

<p>Program Counter (PC) (A)</p> Signup and view all the answers

Which of the following best describes the function of the Stack Pointer (SP) during interrupt handling?

<p>It manages the memory area used for saving the program's state. (A)</p> Signup and view all the answers

What is the role of the Processor Status Register (PSR) during a context switch or interrupt handling?

<p>It stores information about the current state of the CPU, including interrupt enable/disable flags and processor mode. (D)</p> Signup and view all the answers

Flashcards

CPU

The central processing unit that executes instructions.

RAM

Random Access Memory; volatile memory used for active data storage.

I/O Devices

Devices for input/output operations (e.g., keyboard, monitor).

Interrupt Vector

A region in memory containing interrupt handlers.

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Program Counter (PC)

Points to the next instruction to be executed.

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Stack Pointer

Points to the top of the stack.

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Processor Status Register

Contains status information about the CPU.

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Memory Management Unit (MMU)

Hardware that manages memory access and protection.

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ALU Basic Instruction Cycle

Fetch instruction, increment PC, execute instruction.

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User Mode

Allows execution of most instructions, excluding I/O.

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Kernel Mode

Allows execution of all instructions, including I/O and memory access control.

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Interrupt Service Routine (ISR)

A dedicated routine to handle a specific interrupt.

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Shared Memory

Memory area accessible by multiple processes for data sharing.

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Process Table Entry

Data structure containing information about a process.

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Run Queue

A queue of processes ready to be executed.

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Context Switch

Switching from one running program to another, saving the current state to resume later.

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Interrupt

Hardware-generated jump to a subroutine requested by an external device.

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Interrupt Steps

Saving PC on stack, switching to kernel mode, loading PC from vector, saving registers, and resuming execution.

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Critical Section

A section of code that accesses shared data between multiple threads of control.

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Shared Data

Data shared between two or more threads of control where one may be an interrupt, process or thread.

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Block Devices

Devices that read/write data in chunks.

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Program State

Saving the program counter, registers, status register, and stack pointer.

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Hardware Interrupt

A subroutine, requested by an external hardware device, which may be delayed by masking off.

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Saving Interrupt State

Saving PC on stack, switching CPU to kernel, loading PC from vector, and saving all registers.

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Study Notes

  • Operating Systems primarily manage processes, covering topics in the CIS*3110 course.
  • Parts of a computer commonly include RAM, CPU, and I/O Devices

RAM Organization

  • RAM is structured in physical memory with specific sections.
  • "Zero Page" contains the interrupt vector, I/O and Basic Input/Output System/Read-Only Memory if present, starting from memory address 0x00...00.
  • The top of RAM begins at memory address Ox??...??

Hardware Architecture Tools

  • Key components at the hardware level:
  • Program Counter (PC) to track current instruction.
  • Stack pointer/frame pointer for function call management.
  • Processor status register for system state.
  • General purpose registers for data manipulation.
  • Memory management unit for address mapping and protection.
  • Kernel/user mode to define privilege levels.
  • Interrupts and interrupt vector for handling external events

Interrupt Vector and Service Routines

  • An interrupt vector links hardware devices to specific service routines:
  • Disk service routine is at address 3 with function name discintr(...).
  • CD service routine is at address 2.
  • Mouse service routine is at address 1 with function name mouseintr(...).
  • Keyboard service routine is at address 0.

CPU Instruction Cycle and Processor Status

  • Basic instruction cycle:
  • Fetch instruction pointed to by the PC.
  • Increment the PC.
  • Execute the instruction.
  • This cycle repeats continuously, driving program execution.
  • Processor status is managed via a special register on each CPU.
  • User mode can execute most instructions, excluding I/O operations.
  • Kernel mode can execute all user instructions, plus special instructions for I/O and memory access, often referred to as supervisor mode.
  • Interrupt vector is a special range of RAM locations, used to link hardware interrupts to interrupt service routines.

Process and Interrupt Visualization

  • Processes (P1, P2, P3, P4) operate in User Space.
  • They interact with the Kernel Space through interrupt or trap.
  • Kernel Space includes interrupt service routines and hardware interfaces.

Example machine Code Program

  • Sample code program:
  • load R1, OxA2 is represented as machine code 0x11A2, and located at virtual address 0x10.
  • Assembler registers: R0, R1, R2, R3, Stack Pointer (SP), Program Counter (PC)
  • Example Op Codes:
  • load = 0x1
  • store = 0x2
  • incr = 0x3
  • decr = 0x4
  • jmp = 0x5
  • jsr = 0x6
  • rsb = 0x7
  • zero = 0x8

Context Switch

  • A context switch is changing the running program "on the fly".
  • Context switch requires the "program state" to be saved, including:
  • Program counter.
  • General purpose registers.
  • Status register.
  • Stack pointer.
  • Each program must be stored resident in different parts of memory.

Context Switch Timeline

  • A diagram shows the active program interrupted by Disk or Mouse events to trigger a context switch between process, disk and mouse,

Interrupts

  • Interrupts: hardware-generated jump to a subroutine (JSR) requested by an external hardware device.
  • Defined through the interrupt vector:
  • Stored in physical memory.
  • Function pointers array.
  • Can be delayed by masking off.

Interrupts Handling

  • Interrupt actions include:
  • Save Program Counter (PC) on stack.
  • Switch CPU to kernel (supervisor) mode.
  • Load PC from vector using hardware ID.
  • Vector contains interrupt service routine.
  • Save all registers, then continue execution.
  • Return from Interrupt (RTI) includes:
  • Restore registers, then restore saved PC value.
  • Set CPU to previous mode

Critical Sections and Shared Data

  • A critical section has shared data references between threads.
  • Critical sections can involve interrupts, processes, or multiple threads.
  • Data use by all parties must be managed to ensure it is reliable.
  • Failing to correctly manage data may lead to corruption or it being wrong for some processes.
  • Example shows an increment operation i++ represented as a load, increment, and store sequence.

Device Drivers

  • Device drivers are classified into three types in UNIX-type systems:
  • BLOCK: For devices that read/write blocks (disk, tape, SD card, CD/DVD).
  • NETWORK: For local area networks (Ethernet, token ring) and remote connection network interfaces (PPP, ISDN).
  • CHARACTER: For devices that do not fit the above two categories (serial ports, keyboards, mice, joysticks, touchscreens).

Device Driver Functions

  • Top Half (communicates with user, kernel):
  • probe: Checks for hardware during boot.
  • open: Called when a process opens a device file, initialises variables and may generate a user space file descriptor.
  • close: Called on close(), to file descriptor and marks the device as closed.
  • read: Reads data from the device.
  • write: Queues data for device output.
  • Bottom Half (event handling):
  • interrupt service routine: Called when a device generates an interrupt; handles I/O on the hardware.

Device Driver Skeleton - Read Mode

  • Device driver skeleton includes static character queue Q[QSIZE].
  • Reads data from a queue with a limit to is size

Device Driver Skeleton - Interrupt Mode

  • Device driver skeleton includes the GET_CHAR_FROM_DEVICE() function and manages queue operations by sending a signal to wake up a device read.

Running Programs

  • Executing a program leads to a process.
  • Simplified environment provided by the operating system for program execution.
  • UNIX/Mach process environment includes:
  • Virtual (simplified) address space.
  • Process context.
  • Requires no direct access to I/O ports.

Process Table Entry

  • The process table stores an entry for each current process.
  • Each process has its own entry in the process table, if a process has multiple threads.
  • Each entry holds all the information about a process:
  • Process context for program counter, registers, stack pointer, and references to virtual address space.
  • Scheduling information with status flags for BLOCKED, RUNNABLE, and RUNNING, along with priority and time used.

Process Listing Details

  • Process listings that show relevant info like User, Process ID, CPU percentage, Memory use.
  • Listing also provides Virtual memory Size (VSZ), Resident Set Size (RSS), Terminal type (TTY).
  • Also displays the current states STAT, start time as well as the specific command

Synchronization Primitives

  • Shared data between processes/threads requires critical section management.
  • Two common synchronization primitives:
  • mutex: brackets the critical section, to allow maximum one process at a time.
  • semaphores: Allows N number of processes at a time.
  • Co-operating sequential processes can be envisioned as a separate, dedicated processor, with no time guarantees when they run.

Mutex Synchronization

  • Producer adds to a queue using critical_begin() and critical_end().
  • Consumer deletes from a queue using critical_begin() and critical_end().

Mutual Exclusion Implementation

  • Mutual exclusion in hardware manages concurrent access using mutex flags.

Dekker's Algorithm

  • Dekker's algorithm manages mutual exclusion between two processes using need and turn variables.

Semaphores

  • Semaphores synchronize internal integer counters that support signal to increment an internal counter, and wait until value is more than zero, then reduce the counter.

Semaphore Implementation Using Mutexes

  • Semaphore functions which implement SEM_WAIT and SEM_SIGNAL using mutexes for process synchronization.

Semaphore Producer/Consumer

  • Producer and consumer processes use semaphores for synchronization.

Semaphore Hints

  • All semaphores need to be properly initialized.
  • Follows from wait_sem() and signal_sem() definitions.
  • There will be a wait_sem correlated with signal_sem() on the same semaphore
  • Order for wait_sem() operations is important and signal order is less so.

Deadlock Condition

  • Deadlock is created when processes hold the same resources and need new ones held by the other
  • A cycle in request allocations shown on graph indicate deadlock

Java synchronized Keyword

  • The “synchronized” keyword be applied on a whole method or specific block to ensure single access control.

IPC (Inter-Process Communication)

Common processes:

  • Shared Memory: shared process image blocks.
  • Semaphores/Mutexes: integers to control flow .
  • Signals: software “interrupts”.
  • Pipes: shared imitation files between two processes.

Signals in Process Communication

  • Signals indicate the happening of significant event and its sequence:
  • -Process A’ starts and carries out a task. B sends a signal. A interrupts its task and begins managing this incoming signal.
  • -The call of a signal handler (function).
  • -The return of process A is to what task it originally took on.
  • -Process B receives no notification.

Signal value usage

  • Signals: integer-based actions, like interrupts:
  • -Signals (left column) generally take a constant number.
  • -Signals (right column) can vary IDs that depend on the OS

Signal Example Code

  • A code example shows how signals are used for sending command interrupts to performing clean up, which calls the signal

Pipes in programing

  • Pipes join a pair of file descriptors that are shared between processes, bound to a buffer that all processes use. The buffer lives in memory, and is not on the file system.

Scheduling

  • Processes follow the basic scheduler loop:
  • -Process halt or wait.
  • -The “process table entry” saves process.
  • -The table is then “checked”.
  • -Context of operations are restored."
  • -This system part is completed like the “hardware” tasks.

Discipline

  • FIFO: The jobs and/or process join the queue and the repeated joining is called “round robin.” Also, its preemptive.
  • SJF:
  • “First” lists jobs and the running time and those jobs are ahead in the queue at head. Also, its non- preemptive.
  • Discipline is when a part is preemptive before it is done.

Scheduling Algorithms: Queuing Disciplines

  • FIFO along with “round robin": fair, as jobs do not need wait.
  • SJF is w.r.t. output:
  • -If the running job proceeds at shortest “time.”
  • -If the number finished jobs go to the set time compared to all “orders”.
  • -Processes can be approached with its unjust attributes.

Scheduling Disciplines

  • Preemptive planners are better because they are smooth in “response” when compared to non- preemptive and necessary for interactive systems. -Timers have “trade-offs": High better interactive and poor interactive.

Scheduling Algorithms: Queuing

  • Preemption takes short shared-time and is titled “processor sharing."
  • Discipline here, it will always use “FIFO."

Scheduling tasks

Task-scheduling has these forms:

  • -Batch: Tasks completed regardless of “errors."
  • -interactive: Runtime “sensitive” with high “I/O."
  • -Realtime: CPU at limited timings.

Queue priorities

  • -Those systems shift those priorities from system.

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Explore CPU architecture focusing on the roles and functions of various registers. Includes the program counter, stack pointer and processor status register. Learn how these registers manage program execution and handle interrupts.

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