Podcast
Questions and Answers
In a Von-Neumann Architecture, which of the following is a characteristic?
In a Von-Neumann Architecture, which of the following is a characteristic?
- Shared bus for data and instructions (correct)
- Dual core processing
- Separate buses for data and instructions
- Separate memory spaces for data and instructions
What is the main purpose of Instruction Pipelining?
What is the main purpose of Instruction Pipelining?
- To increase clock speed
- To achieve higher execution speed at the same clock speed (correct)
- To increase parallel processing
- To reduce instruction latency
What happens to the Stack Pointer during the first PUSH operation?
What happens to the Stack Pointer during the first PUSH operation?
- It points to a location outside SRAM
- It points to a random memory location in SRAM
- It points to the first memory location in SRAM
- It points to the last memory location in SRAM (correct)
What is the Instruction Life Cycle?
What is the Instruction Life Cycle?
What type of architecture do microcontrollers most often use?
What type of architecture do microcontrollers most often use?
What is the benefit of Instruction Pipelining?
What is the benefit of Instruction Pipelining?
What is the purpose of the Stack Pointer?
What is the purpose of the Stack Pointer?
In a Harvard Architecture, what is the main difference from Von-Neumann Architecture?
In a Harvard Architecture, what is the main difference from Von-Neumann Architecture?
What happens to the Stack Pointer after a POP operation?
What happens to the Stack Pointer after a POP operation?
What is the main advantage of using a Harvard Architecture in microcontrollers?
What is the main advantage of using a Harvard Architecture in microcontrollers?
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Study Notes
Central Processing Unit (CPU)
- The CPU has several units: Instruction Decoder (Control Unit), Accumulator Register, Register File, Arithmetic Logic Unit (ALU), and SFR Registers.
- The Instruction Decoder (Control Unit) converts instructions from program memory into a format the ALU can understand and generates control signals.
Instruction Decoder (Control Unit)
- Controls the flow of data through the processor and coordinates the activities of other units.
- Generates control signals for the ALU and Register File.
Accumulator Register
- A working desk for storing data for operations like addition, shift, and subtraction.
- Closely related to the operation of the ALU.
Register File
- A group of registers (e.g., 32 registers R0-R31 in AVR CPU).
- Can read two registers at once by supplying addresses and writing to a register using data inputs and setting WR=1.
Instruction Cycle
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- Decode Instruction: Control Unit generates control signals for the ALU and Register File.
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- Execute Instruction: ALU executes the instruction.
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- Write Back Instruction: Control Unit generates control signals to store the result in the Register File.
Arithmetic Logic Unit (ALU)
- Part of the CPU responsible for performing calculations and executing arithmetic, logic, and shift instructions.
- Arithmetic instructions: addition, subtraction, shifting operations.
- Logic instructions: AND, OR, XOR, NOT operations.
Stack Pointer and Stack Operations
- The Stack Pointer must be initialized to point to the last memory location in SRAM.
- PUSH and POP operations update the stack.
Instruction Pipelining and CPU Architecture
- Instruction Pipelining: continuous and parallel streaming of instructions to the CPU for higher execution speed at the same clock speed.
- The AVR CPU uses a modified Harvard Architecture with parallel instruction fetches and executions.
- CPU Architecture: Von-Neumann and Harvard architectures exist, with microcontrollers often using a Harvard or modified Harvard-based architecture.
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