CPU Architecture Basics

CPU Architecture

Components

• Control Unit: retrieves and decodes instructions, generates control signals to execute instructions
• Arithmetic Logic Unit (ALU): performs arithmetic and logical operations
• Registers: small amount of on-chip memory that stores data temporarily

Instruction Cycle

1. Fetch: retrieve instruction from memory
2. Decode: decode instruction into opcode and operands
3. Execute: execute instruction using ALU and registers
4. Store: store results in registers or memory

CPU Execution

• Pipelining: breaking down instruction cycle into stages to increase throughput
• Superscalar Execution: executing multiple instructions simultaneously
• Out-of-Order Execution: executing instructions out of original order to improve performance

CPU Design Considerations

• Performance: measured in clock speed (GHz), instructions per clock (IPC), and instructions per second (IPS)
• Power Consumption: measured in watts (W), affects battery life and heat generation
• Cost: affects manufacturing cost and affordability

CPU Architectures

• CISC (Complex Instruction Set Computing): uses complex instructions that perform multiple operations
• RISC (Reduced Instruction Set Computing): uses simple instructions that perform single operations
• MISC (Minimal Instruction Set Computing): uses minimal instructions that perform basic operations

CPU Technologies

• Multithreading: executing multiple threads simultaneously to improve performance
• Multiprocessing: using multiple CPUs to improve performance
• Virtualization: running multiple virtual machines on a single CPU

CPU Architecture

Components

• Control Unit retrieves and decodes instructions, generating control signals to execute them
• Arithmetic Logic Unit (ALU) performs arithmetic and logical operations
• Registers are a small amount of on-chip memory that stores data temporarily

Instruction Cycle

• The instruction cycle consists of four stages: fetch, decode, execute, and store
• Fetch retrieves an instruction from memory
• Decode decodes the instruction into opcode and operands
• Execute executes the instruction using the ALU and registers
• Store stores the results in registers or memory

CPU Execution

• Pipelining breaks down the instruction cycle into stages to increase throughput
• Superscalar Execution executes multiple instructions simultaneously
• Out-of-Order Execution executes instructions out of their original order to improve performance

CPU Design Considerations

• Performance is measured in clock speed (GHz), instructions per clock (IPC), and instructions per second (IPS)
• Power consumption is measured in watts (W) and affects battery life and heat generation
• Cost affects manufacturing cost and affordability

CPU Architectures

• CISC (Complex Instruction Set Computing) uses complex instructions that perform multiple operations
• RISC (Reduced Instruction Set Computing) uses simple instructions that perform single operations
• MISC (Minimal Instruction Set Computing) uses minimal instructions that perform basic operations

CPU Technologies

• Multithreading executes multiple threads simultaneously to improve performance
• Multiprocessing uses multiple CPUs to improve performance
• Virtualization runs multiple virtual machines on a single CPU