CPU Architecture and Components

CPU Architecture

• In 1945, mathematician Von Neumann developed a theoretical framework for the concept of a computer
• According to Von Neumann, a computer should have:
  • A central processing unit (CPU).
  • A main memory (RAM) to store instructions and data.
  • Input/output devices.

CPU Structure

• The CPU comprises several registers, the control unit (CU), and the arithmetic logic unit (ALU)
• Registers facilitate quick access to frequently used data and instructions
• The CU fetches instructions from memory, decodes them, and coordinates their execution
• The ALU performs arithmetic and logical operations

CPU Components

• The Arithmetic Logic Unit (ALU) handles arithmetic (addition, subtraction) and logical operations
• The Control Unit reads instructions from memory (using the Program Counter) and synchronizes all computer elements
• The System Clock generates timing signals needed for correct operation by sending signals through the control bus
• Immediate Access Store (IAS) is another name for RAM and stores data for execution although not a element of the CPU itself

Registers

• Registers are small, high-speed storage areas within the CPU with specific or general purposes in data storage
• Current Instruction Register (CIR) stores the instruction being executed
• Index Register (IX) facilitates indexed addressing
• Memory Address Register (MAR) holds the memory address to be read from or written to
• Memory Data/Buffer Register (MDR or MBR) stores data read from the address in MAR or to be written to that address
• Program Counter (PC) stores the address of the next instruction to be read
• Status Register (SR) stores bits indicating the operation states

Status Register

• The status register contains 4 bits, each corresponding to a situation in the ALU:
  • Carry flag: Set to 1 if a binary addition results in a carry bit.
  • Negative flag: Set to 1 if the result is negative.
  • Overflow flag: Set to 1 if there is an overflow where summing positive numbers is a negative number
  • Zero Flag: Set to 1 if the result is 0.

Buses

• Buses in computing send and receive information to/from the CPU, as well as, transfer data and addresses for CPU operation
• The three main buses in the Von Neumann architecture are the address bus, the data bus, and the control bus

Bus Types

• The address bus transfers data regarding particular places in memory for CPU operation, functioning unidirectionally
  • Address bus width (number of bits handled) determines the memory locations accessible
    • A 32-bit bus allows up to 4GB of RAM, while a 64-bit bus allows 16 exabytes (17,179,869,184 GB) of RAM
• The data bus transfers required data to the CPU bidirectionally
  • The direction of a data entry is transferred thru the data bus not the address bus
• The control bus is bidirectional and carries signals from the CU to computer components
  • A CPU sends a signal through control bus for each cycle

Ports

• Input/output devices connect to the computer using ports, with the Control Unit managing their interaction
• Examples: USB, VGA, HDMI

Ports Explained

• Universal Serial Bus (USB) is an asynchronous data transmission protocol
  • USB cables have 4 smaller cables: two for current (+ and -) and two for data transmission.
  • Computers recognize USB connections, automatically loading drivers or prompting to download them as needed
• High-Definition Multimedia Interface (HDMI) transfers audio and video from the computer to a display
  • HDMI was developed because VGA does not transfer the necessary amount of data modern screens require.
  • HDMI can safeguard against piracy using HDCP.
• Video Graphics Array (VGA) - outdated technology allowing resolutions up to 640 x 480 rapidly replaced by HDMI

Fetch-Execute Cycle

• Instructions reach the processor and are executed in two parts, first receiving the instruction and the executing it

Fetch-Execute Cycle - Fetch

• The processor requests the instruction from the address stored in the Program Counter (PC), saves it in the CIR, increments the PC by 1, and decodes stored instruction

Fetch-Execute Cycle - Execute

• The CPU interprets the instruction and sends control signals to the components needed for execution

Fetch-Execute Cycle - RTN

• Register Transfer Notation (RTN) describes each step when using registers
  • F-E cycle in RTN:
    • MAR <- [PC] (copy PC contents to MAR)
    • PC <- [PC] + 1 (increment PC by 1)
    • MDR <- [[MAR]] (explained shortly)
    • CIR <- [MDR] (copy MDR contents to CIR)
• Brackets [] signify reference to the data within the register
  • MDR <- [[MAR]], double brackets are used because MAR stores an address and access entails the data at that address

Interrupts

• An interrupt is a signal sent from a device/software to the CPU, prompting the CPU to pause to handle an event

Interruptions Explained

• Interrupts arise from input/output devices (keyboard), hardware errors, and software errors, with assigned priorities and are handles in order of importance
• After handling the interrupt, the CPU continues executing instructions

Assembly Language

• The only language understood by CPUs machine code which is simpler than most programming languages
• Programs written in Python use a compiler to translate the code into machine language readable by CPU
• Each CPU model has its own set of instructions, for example, saving a value at a specific place in computer memory
• All instructions have an opcode and operands.

Assembly Stages

• An assembler program translates opcodes and operands to binary and verifies the instruction order
• Single-pass assemblers store the program directly in memory
• Two-pass assemblers generate a separate executable program, providing program flexibility and a loader program

Assembly Instructions

• Assembly instructions may be: data movement, input/output, arithmetic operations, jumps, or comparisons

Data Movement Instructions

• Using two registers, Accumulator and IX, with accumulators storing operation data and the IX which is utilized for index numbering

Data Movement Operation Codes

• LDM #n: Stores the number n in the ACC
• LDD : Stores the content at the address in the ACC
• LDI : Stores the content of the address stored in the address in the ACC
• LDX : Stores the content at the address + IX in the ACC
• LDR #n: Stores n in IX
• LDR ACC: Stores the data of ACC in IX
• STO : Stores the contents of the ACC at the address

Input / Output

• There are two opcodes:
  • IN: Inputs a value and stores its ASCII in ACC
  • OUT: Displays the character whose ASCII value is stored in ACC

Arithmetic Instructions

• Results from arithmetic operations are stored in the ACC
  • ADD : Adds contents of with the ACC
  • ADD #n: Adds n to the ACC
  • SUB : Subtracts contents of from the ACC
  • SUB #n: Subtracts n from the ACC
  • INC : Adds 1 to (ACC or IX)
  • DEC : Subtracts 1 from (ACC or IX)

Jump instructions

• Jump instructions change the PC number to the given address, affecting the next instruction executed
  • JMP : Jumps to address
  • JPE : Jumps if comparison is TRUE.
  • JPN : Jumps if comparison is FALSE.

Comparison Instructions

• Comparison instructions are used with jumps
  • CMP : Compares the contents of ACC with the location at
  • CMP #n: Compares ACC with n
  • CMI : Compares ACC with the data within the address

Addressing

• Addressing indicates where to retrieve operational data, related to data movement instructions
• Addressing types include Absolute, Direct, Indirect, Indexed, Immediate, Relative, and Symbolic

Addressing Types

• Direct Addressing: LDD 200 stores the number 20 in ACC
• Indirect Addressing: LDI 200 stores the number 5 in ACC
• Indexed Addressing (IX=4): LDX 200 stores 17 in ACC
• Immediate Addressing: LDM #200 stores 200 in the ACC

Manipulation of Bits

• The binary shift moves bits stored in a register a certain number of places with differing effect

Kinds of Binary Shift

• Logical Shift: Bits leaving the register are replaced by 0.
• Arithmetic Shift: The sign of the number is maintained.
• Cyclic Shift: Bits leaving one side of the register enter from the other.
• All of these shifts may be move bits to the left of the right

Results of Binary Shift Example

• For a register with a binary value of 10101111:
  • Logical Shift to the left by 3 places: 01111000.
  • Arithmetic Shift to the right by 3 places: 11110101.
  • Cyclic Shift to the left by 3 places: 01111101.

Assembly Opcodes for Corrimiento de Bits (Bit shifting)

• LSL n: Logical Shift to the left n places.
• LSR n: Logical Shift to the right n places.

Bit Monitoring and Control

• Monitoring and control identify each bit in a register separately, utilizing logical operations
  • AND gate can determine if a bit is 1 or 0.
  • OR gate sets a bit to 1.
  • XOR gate sets a bit to 0.

Assembly Instructions for Bit Monitoring and Control

• AND n: AND the contents of the ACC and n.
• AND : AND the contents of the ACC and the contents of .
• XOR n: XOR between ACC and n.
• XOR : XOR between the ACC and the content of .
• OR n: OR between ACC and n.
• OR : OR between ACC and content of .