Computer Systems Structure - The CPU
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What is the first phase of the simple computer operation?

  • Instruction fetch (correct)
  • Decode the instruction
  • Prepare execution
  • Execute

    • The simple computer has two registers: the accumulator and the instruction register.

    False

    What does the term 'PC' stand for in the context of a simple computer?

    Program Counter

    In the simple computer, the _______ phase prepares for the execution by reading data from memory.

    <p>PreEx</p> Signup and view all the answers

    Match the following components of a simple computer with their functions:

    <p>IR = Stores the current instruction Acc = Holds the arithmetic results PC = Tracks the address of the next instruction ALU = Performs arithmetic and logic operations</p> Signup and view all the answers

    What are the two components of the von Neumann’s classical model incorporated in the CPU?

    <p>ALU and CU</p> Signup and view all the answers

    The CPU can execute instructions in a sequential order only.

    <p>False</p> Signup and view all the answers

    What role does the Control Unit (CU) play in the CPU?

    <p>It directs the operation of the processor by managing and coordinating the activities of the CPU.</p> Signup and view all the answers

    The CPU is described as the brain of the computer, responsible for tasks like fetch, decode, execute instructions, and store the ______.

    <p>result</p> Signup and view all the answers

    Match the following components of the CPU with their descriptions:

    <p>ALU = Performs arithmetic and logic operations CU = Controls the execution of instructions Cache Memory = Provides fast access to frequently used data Bus Controller = Manages data transfer between components</p> Signup and view all the answers

    What is the CPI for sequential execution in the given content?

    <p>5</p> Signup and view all the answers

    In ideal pipelined execution, the CPI can reach 0.

    <p>False</p> Signup and view all the answers

    What is the main advantage of superscalar architecture?

    <p>Multiple pipelines allow for more than one instruction to be executed simultaneously.</p> Signup and view all the answers

    In superpipeline architecture, each phase requires only half a ______ to complete.

    <p>clock period</p> Signup and view all the answers

    Match the architectures with their characteristics:

    <p>Superscalar = Multiple pipelines for instruction execution Superpipeline = Phases require only half a clock period Sequential execution = Single pipeline with higher CPI Pipelined execution = Ideal CPI of 1</p> Signup and view all the answers

    What type of architecture allows fetching 2 instructions every clock cycle?

    <p>Superscalar</p> Signup and view all the answers

    The pipelined MIPS architecture allows for greater efficiency by overlapping instruction phases.

    <p>True</p> Signup and view all the answers

    What is the CPI of a perfectly optimized superpipeline architecture?

    <p>0.5</p> Signup and view all the answers

    What is a benefit of static scheduling?

    <p>It is executed only once for the entire execution.</p> Signup and view all the answers

    Dynamic scheduling helps to reduce the effects of hazards during program execution.

    <p>True</p> Signup and view all the answers

    What are the two types of scheduling methods mentioned?

    <p>Static scheduling and dynamic scheduling</p> Signup and view all the answers

    The ______ technique involves rearranging instructions to minimize delays caused by hazards.

    <p>dynamic scheduling</p> Signup and view all the answers

    Which of the following is a method to detect and address hazard cases?

    <p>Stall phases</p> Signup and view all the answers

    Branch prediction is a static method of scheduling.

    <p>False</p> Signup and view all the answers

    List one advantage of dynamic scheduling.

    <p>The processor can optimize based on its knowledge of its own structure.</p> Signup and view all the answers

    Match the following terms to their descriptions:

    <p>Static Scheduling = Established beforehand by the compiler. Dynamic Scheduling = Reorders instructions during execution. Stall Phases = Introduced to manage hazard cases. Branch Prediction = Predicts the outcome of branching instructions.</p> Signup and view all the answers

    What is the result of the following operation in example 1: ADD Acc, M[100h]?

    <p>Acc is increased by the value in M[100h]</p> Signup and view all the answers

    In the MIPS architecture, instructions are of variable length.

    <p>False</p> Signup and view all the answers

    What type of hazard occurs due to data dependency between consecutive instructions?

    <p>Data hazard</p> Signup and view all the answers

    What operation is performed when the instruction SHR Acc is executed?

    <p>Shift the accumulator one position to the right</p> Signup and view all the answers

    In the MIPS architecture, the instruction fetch phase is abbreviated as ______.

    <p>IF</p> Signup and view all the answers

    A write after read (WAR) hazard is common in classic pipeline architectures.

    <p>False</p> Signup and view all the answers

    Match the following phases of instruction execution in the MIPS architecture:

    <p>IF = Instruction Fetch ID = Instruction Decode Ex = Execute M = Memory Operation Wb = Write Back</p> Signup and view all the answers

    What is a solution to manage data hazards that involves the instruction waiting until the necessary data is available?

    <p>Stall phases</p> Signup and view all the answers

    Which of the following best describes the Harvard memory architecture?

    <p>Separate memory space for instructions and data</p> Signup and view all the answers

    A __________ hazard occurs when two instructions intend to write to the same register.

    <p>write after write (WAW)</p> Signup and view all the answers

    The MOV instruction transfers data between memory and the accumulator.

    <p>True</p> Signup and view all the answers

    Match the hazard types with their correct descriptions:

    <p>RAW = Read after write WAR = Write after read WAW = Write after write RAR = Read after read</p> Signup and view all the answers

    What does the acronym PC stand for in the context of computer architecture?

    <p>Program Counter</p> Signup and view all the answers

    Which of the following is NOT a type of data hazard?

    <p>RAX</p> Signup and view all the answers

    Structural hazards can occur when two instructions in different phases use the same structural component.

    <p>True</p> Signup and view all the answers

    The conditional jump in the architecture relies on checking the value in the ______.

    <p>Accumulator</p> Signup and view all the answers

    What is the primary function of the Control Unit in a computer?

    <p>Manage and coordinate the activities of the CPU</p> Signup and view all the answers

    What technique allows for transferring a result in advance before it is officially written to its final location?

    <p>Forwarding</p> Signup and view all the answers

    The use of __________ allows instructions with no logical dependency to get different copies of the same register, helping to avoid data dependency issues.

    <p>register renaming</p> Signup and view all the answers

    Out-of-order execution is also known as what type of execution?

    <p>Speculative execution</p> Signup and view all the answers

    Study Notes

    Computer Systems Structure - The CPU

    • The CPU (Central Processing Unit) is the brain of a computer, performing core tasks
    • A "classic" view incorporates the ALU (Arithmetic Logic Unit) and CU (Control Unit), two of the five components of the von Neumann model
    • The CPU fetches, decodes, and executes instructions, processing data in a synchronized and sequential manner
    • Modern CPUs contain complex components like multiple CPUs (symmetric/asymmetric), multiple cores, multiple ALUs (e.g., floating-point, multimedia), various levels of cache memory, memory management units, and peripheral device interfaces
    • CPUs today handle diverse components like serial channels, parallel interfaces, timers, counters, converters (ADC, DAC), network interfaces, interrupt systems, bus controllers, and arbiters

    Simple Computer Attributes

    • A simple computer has sequential processing, with one accumulator register and one memory for instructions and data
    • Components include a clock generator (CG), phase generator (PhG), instruction register (IR), address register, memory, data input/output, control signals, an arithmetic logic unit (ALU), and an accumulator
    • Instructions execute in four phases:
      • IF (Instruction Fetch): Reads the instruction into the IR
      • Dec (Decode): Decodes the instruction and generates control signals
      • PreEx (Prepare Execution): Prepares for execution, e.g., reads data from memory
      • Exe (Execute): Executes instructions like adding or subtracting operations

    Simple Computer Examples

    • Example instructions: ADD Acc, M[100h], JMP 200h, SHR Acc
    • IF: instruction fetch, assigns address to PC
    • Dec: sets address according to instruction register
    • PreEx: defines the operation for the ALU
    • Exe: executes given opcode calculation with the contents

    MIPS Architecture

    • MIPS (Microprocessor without Interlocked Pipeline Stages) is a more sophisticated computer architecture
    • Attributes: 32 16-bit registers, fixed-length instructions, separate instruction and data memory ("Harvard architecture")
    • Instructions execute in five stages (IF, ID, Ex, M, Wb):
      • IF: Fetches the instruction
      • ID: Decodes the instruction, reads register values
      • Ex: Executes the ALU operation
      • M: Memory access (if needed)
      • Wb: Writes the result back to a register
    • Instruction Types: R (register), I (immediate), J (jump) with examples of assembly syntax (ex: ADD $RS, $RD,$RT ; ADDI $RT,$RS, constant; JMP target)

    MIPS Architecture - Instruction Formats

    • Instructions have fixed length (4 bytes)
    • "R" instructions specify registers with fields for source/destination registers and function code
    • "I" instructions specify immediate values using an additional field
    • "J" instructions specify jump targets using a field for the target address

    MIPS Architecture - Address Generation & Instruction Fetch

    • The PC (program counter) is incremented by 4 after fetching an instruction
    • Jump and branch instructions update the PC directly

    MIPS Architecture - Decode & Data Preparation

    • The instruction is decoded
    • Data are read from the register file and from immediate value (if applicable)

    MIPS Architecture - Execute & Memorize

    • The ALU (Arithmetic Logic Unit) performs the instruction's operation
    • Memory writes and reads happen (if needed)

    MIPS Architecture - Write Back Result

    • The results of the instruction are written back to the appropriate register in the register file

    MIPS Architecture - Pipeline Execution

    • Pipelining increases execution speed by overlapping instruction execution steps, increasing clock frequency
    • Superscalar: Multiple pipelines for multiple instructions per clock cycle, increasing speed
    • Superpipelining: Shortening individual pipeline stages to increase processing rate

    Pipeline Architecture - Hazard Cases

    • Hazards (data, control, structural) reduce pipeline efficiency
    • Data hazards: dependencies between instructions (read-after-write, write-after-read)
    • Control hazards: conditional branches in instructions causing stalls
    • Structural hazards: multiple instructions accessing the same resource simultaneously, causing stalls
      • Solutions, e.g, forwarding , dynamic scheduling, static scheduling, pipe-lining, branch predictions

    Static vs. Dynamic Scheduling

    • Static scheduling: Compiler reorders instructions before execution to reduce hazards
    • Dynamic scheduling: Processor reorders instructions during execution for better optimization

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    Description

    This quiz covers the central processing unit (CPU), exploring its critical functions within computer systems. It examines the von Neumann model, the role of the arithmetic logic unit (ALU), control unit (CU), and modern CPU complexities. Additionally, it discusses simple computer attributes and components.

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