Computer Systems Structure - The CPU

In a computer system, the Instruction Fetch (IF) phase involves retrieving the next program instruction from memory and loading it into the Instruction Register (IR).

The Decode phase in a computer system's instruction cycle is where the instruction is analyzed and interpreted, generating specific 'control signals' that guide the subsequent execution steps.

The Prepare Execution (PreEx) phase in a computer's instruction cycle involves actions needed before the actual execution takes place. This often includes data fetching from memory or setting up registers for calculations.

The Execute phase in a computer's instruction cycle is where the actual operation defined by the instruction takes place, involving calculations, data manipulations, or other operations.

A simplified computer model often described as having a single accumulator register to perform calculations and limited memory for instructions and data.

The brain of a computer, responsible for fetching, decoding, reading data, executing instructions, and storing results. It operates in a synchronized, sequential manner, handling one task at a time.

The CPU in modern systems includes multiple components beyond the ALU and Control Unit. This includes multiple CPUs, cache memory, interfaces, peripherals, interrupt system, bus controllers, and memory management units.

The Arithmetic Logic Unit (ALU) is responsible for performing mathematical operations (addition, subtraction, multiplication, etc.) and logical operations (AND, OR, NOT) on data.

The Control Unit (CU) is responsible for fetching instructions from memory, decoding their meaning, and directing the rest of the CPU to execute them.

The CPU can execute instructions in parallel and in a speculative order, meaning it can start working on the next instruction before the previous one is finished, based on predictions.

Pipeline execution is a technique that breaks down the execution of an instruction into a sequence of smaller steps, allowing multiple instructions to be executed concurrently.

Clock cycles per instruction (CPI) measures the average number of clock cycles required to execute one instruction.

Sequential execution refers to executing instructions one after the other, without any overlapping.

A superscalar architecture utilizes multiple execution units, allowing it to fetch and execute multiple instructions simultaneously in a single clock cycle.

A superpipeline architecture reduces the clock cycle period for each phase of the pipeline, allowing for faster execution.

In the ideal case of a pipeline, the CPI is 1, meaning each instruction takes only one clock cycle to complete.

MIPS is a Reduced Instruction Set Computing (RISC) architecture that has been widely used in processors.

A register-to-register instruction operates on data stored in registers (temporary storage locations) within the processor.

A type of computer instruction that performs an addition operation, adding the contents of the accumulator register to the value stored in a memory location.

A type of computer instruction that moves data from a memory location to the accumulator register.

A type of computer instruction that moves data from the accumulator register to a memory location.

A type of computer instruction that jumps to a specified memory address, changing the program's execution path.

A type of computer instruction that performs a right shift operation on the accumulator register, effectively dividing its value by two.

A computer architecture that uses separate memories for storing instructions and data, improving performance by allowing simultaneous access to both types of information.

A sequence of operations performed by a computer to execute a single instruction, including phases like fetching, decoding, execution, memory access, and write-back.

A type of computer instruction that performs an operation based on a condition, modifying the program's flow based on the result.

A type of computer architecture that uses a set of internal registers to hold data, making it faster to access and manipulate compared to accessing data directly from memory.

A part of a computer responsible for decoding instructions and controlling the execution of other components, essentially the brain of the computer.

A hazard in a pipeline architecture occurs when one instruction depends on the result of a previous instruction that hasn't finished executing yet. This creates a delay, as the dependent instruction has to wait for the previous one to complete.

A method used to bypass the effects of hazards by inserting temporary 'stall' phases (pauses) into the pipeline execution. This gives time for the dependent instruction to wait for the previous one to complete.

A technique for predicting the outcome of a branch instruction (like 'if' statements) to reduce delays. It predicts whether the branch will be taken or not, allowing the pipeline to proceed without waiting for the actual outcome to determine the next instruction.

A technique where instructions are allowed to execute in a different order than they were written, as long as the logical dependencies are preserved. This reduces the impact of hazards by allowing instructions that don't depend on each other to proceed concurrently.

A way of arranging instructions before execution to minimize the chance of hazards. It's typically done by the compiler or user, often based on insights about the structure of the pipeline.

A way of arranging instructions during execution to minimize the chance of hazards. It relies on the hardware to analyze dependencies and reorder instructions dynamically based on the actual execution flow.

A type of dynamic scheduling employed by processors to reorder instructions during execution to reduce the impact of hazards. It allows instructions to proceed in a non-sequential order, maximizing pipeline efficiency.

A type of memory organization used in some CPUs where code instructions and data are stored separately. This separation enables faster instruction fetching and fetching data simultaneously, leading to better performance.

A situation in a pipelined architecture where consecutive instructions depend on each other, causing delays due to the need for data to be available before the next instruction can execute.

A hazard that occurs when a jump or branch instruction changes the normal execution order, causing the pipeline to fetch incorrect instructions.

A hazard that arises when different instructions require the same structural component simultaneously, such as the ALU or memory, causing a bottleneck.

A type of data hazard where an instruction attempts to read data before it has been written by a previous instruction. This is a common occurrence in pipelined execution.

A type of data hazard where an instruction attempts to write data to a register before it has been read by a previous instruction. This is less common in traditional pipelines but more prevalent in superscalar pipelines.

A type of data hazard where an instruction attempts to write data to a register before a previous instruction has finished writing to the same register.

A technique used to solve data hazards in pipelined architectures. It involves transferring a result to the next instruction in the pipeline before it has been written to its final location.

A technique used to solve data hazards by creating multiple copies of registers, allowing instructions with no actual dependency to use different copies.',

A technique used in pipelined architectures where an instruction with an unsolved data dependency is stalled in the "instruction fetch" stage until the required data becomes available. The subsequent instructions also wait.