Computer Systems Structure - CPU Hazards

A method for dynamically scheduling a pipeline to execute instructions out-of-order, avoiding conflicts and utilizing available hardware.

The first stage of the Scoreboard method where the instruction is decoded, checked for structural and write-after-write (WAW) hazards, and stalled if necessary.

The second stage of the Scoreboard method where the instruction waits for read-after-write (RAW) hazards to be resolved before reading operands.

The third stage of the Scoreboard method where the instruction performs the operation on the operands, and may take multiple cycles to complete.

The final stage of the Scoreboard method where the instruction writes the result to the destination register, stalling if a write-after-read (WAR) hazard occurs.

A component of the Scoreboard method that tracks the status of each instruction and functional unit.

A section of the Scoreboard structure that keeps track of the state of the functional unit (FU) – if it is busy, the operation being performed, and source and destination registers.

A section of the Scoreboard structure that indicates which functional unit will write to each register.

A technique for addressing structural hazards in pipelined processors. It uses a set of buffers called reservation stations to hold instructions and their operands, allowing multiple instructions to be active simultaneously.

A specialized hardware unit within a processor that performs floating-point operations such as addition, subtraction, multiplication, and division.

A type of hazard that occurs when multiple instructions require access to the same resource, such as a functional unit or memory location, simultaneously.

A special bus within a processor that allows data to be broadcast to multiple locations simultaneously. This helps avoid unnecessary stalls when waiting for data to be written back to a register.

A technique used in Tomasulo's algorithm to create multiple copies of registers, allowing different instructions to use the same register name without creating data dependencies.

A type of dependency that occurs when an instruction needs to use the result of a previous instruction, but the result is not yet available in the destination register.

A type of dependency that occurs when an instruction needs to write to a register that another instruction is reading from. This can lead to incorrect results unless handled properly.

A type of dependency that occurs when two instructions need to write to the same register. This can lead to incorrect results if the instructions are not executed in the correct order.

Buffers within a pipelined processor that hold instructions and their operands during the execution stages. They allow multiple instructions to be active simultaneously and reduce the need to wait for data dependencies.

An extra stage added to the instruction execution sequence, besides issue, execute and write result, in Tomasulo's algorithm.

A buffer that stores instructions executed out-of-order, allowing for efficient commit in their original order.

A technique used to optimize program execution by predicting the direction of a branch instruction before it is actually executed.

A method of branch prediction based on the nature of the branch instruction itself.

A method of branch prediction that uses the history of branch instructions to make more informed predictions.

A dynamic branch prediction method that stores the pointer to the next instruction or group of instructions, along with the decision and target of the branch.

A dynamic branch prediction method that uses saturating counters to remember the history of each branch.

A table used to store the decision and target address of every executed conditional jump, which helps predict future executions of the same instructions.

A buffer used to store the target address of branches, which can be quickly accessed during branch prediction.

The state associated with each entry in the BTB, indicating whether a branch is likely to be taken or not. This helps the processor make better predictions.

When the processor predicts a branch correctly, it can continue fetching instructions from the predicted target address, allowing it to execute instructions without delays.

When the processor predicts a branch incorrectly, it needs to discard the fetched instructions based on the incorrect prediction and start fetching from the actual branch target. This causes a stall in the pipeline.

A technique where the prediction is based on the recent history of a specific conditional jump instruction. It uses a separate history buffer for each instruction.

A technique where the prediction is based on a shared global history of all conditional jumps. It utilizes correlations between branches for prediction.

A two-level adaptive predictor uses a history buffer (n bits) to track past branch outcomes and a pattern history table to predict future outcomes based on repeating patterns.

A type of global branch predictor where the index into the pattern history table is calculated by XOR-ing the global history buffer with the branch address.

A type of global branch predictor where the index into the pattern history table is constructed by concatenating the global history buffer and the branch address.

A technique that combines local and global branch prediction for a more accurate prediction. It can concatenate local and global histories or make decisions using voting.

A type of branch prediction that specifically targets loop structures. It tracks loop iterations using a counter and may be part of a hybrid predictor.

A challenge in branch prediction where the jump target has multiple possibilities. It requires storing previous targets and using a larger history buffer.

A technique that uses a copy of the stack to store return addresses of executed functions, enabling prediction of function returns without performing actual jumps.

A local branch predictor with a 4-bit history buffer and a 16-entry pattern history table for each conditional jump, used in Pentium II and III processors.

Global branch predictors are used in Pentium M, Core 2, and AMD processors, using either gshare or gselect for index calculation.

A branch prediction technique that combines local and global histories, sometimes with the branch address, for a more accurate prediction.

A prediction approach that XORs the predictions of the local and global predictors, used in Pentium 4, for better accuracy.

A predictor that is part of a hybrid system and detects loop structures, counting loop iterations and using this information for prediction.