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Questions and Answers
What action is taken if the instruction is identified as a non-branch instruction?
What action is taken if the instruction is identified as a non-branch instruction?
What happens when a mispredicted branch occurs?
What happens when a mispredicted branch occurs?
What is the function of the branch-target buffer in this context?
What is the function of the branch-target buffer in this context?
During the instruction decoding phase (ID), what determines if the next action involves a branch?
During the instruction decoding phase (ID), what determines if the next action involves a branch?
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What does the system do if there is an entry found in the branch-target buffer and the instruction is a taken branch?
What does the system do if there is an entry found in the branch-target buffer and the instruction is a taken branch?
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What is the primary purpose of the scoreboard method in CPU architecture?
What is the primary purpose of the scoreboard method in CPU architecture?
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Which stage of instruction processing involves checking for structural and write-after-write (WAW) hazards?
Which stage of instruction processing involves checking for structural and write-after-write (WAW) hazards?
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In the scoreboard structure, what does the 'Busy' status indicate?
In the scoreboard structure, what does the 'Busy' status indicate?
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What must occur before an instruction can proceed to the Read operands stage?
What must occur before an instruction can proceed to the Read operands stage?
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How does the scoreboard handle stalled instructions?
How does the scoreboard handle stalled instructions?
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Which hazard type is checked during the Write result stage of instruction processing?
Which hazard type is checked during the Write result stage of instruction processing?
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What aspect does the 'Register result status' of the scoreboard indicate?
What aspect does the 'Register result status' of the scoreboard indicate?
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In which computer was the scoreboard method first used?
In which computer was the scoreboard method first used?
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What is the role of a Tournament predictor in branch prediction?
What is the role of a Tournament predictor in branch prediction?
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How does the 2-bit local predictor perform when dealing with significant branches?
How does the 2-bit local predictor perform when dealing with significant branches?
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What is included in the Branch Target Buffer (BTB)?
What is included in the Branch Target Buffer (BTB)?
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What is the size of memory used for 1024 entries in a local and global prediction (2,2) BHT?
What is the size of memory used for 1024 entries in a local and global prediction (2,2) BHT?
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What phenomenon occurs when comparing the misprediction rates of different predictors?
What phenomenon occurs when comparing the misprediction rates of different predictors?
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What is a primary benefit of Tomasulo’s algorithm compared to the Scoreboard method?
What is a primary benefit of Tomasulo’s algorithm compared to the Scoreboard method?
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What is a significant limitation of the Scoreboard method?
What is a significant limitation of the Scoreboard method?
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Which distinctive feature does Tomasulo’s algorithm employ to manage data dependencies?
Which distinctive feature does Tomasulo’s algorithm employ to manage data dependencies?
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What hardware component is primarily increased in quantity when implementing the Scoreboard method?
What hardware component is primarily increased in quantity when implementing the Scoreboard method?
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What are reservation stations used for in Tomasulo’s algorithm?
What are reservation stations used for in Tomasulo’s algorithm?
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Which is NOT a feature of Tomasulo’s algorithm?
Which is NOT a feature of Tomasulo’s algorithm?
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What role do redundant functional units serve in Tomasulo's algorithm?
What role do redundant functional units serve in Tomasulo's algorithm?
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Which functional unit is not typically referenced in the context of the P6 architecture?
Which functional unit is not typically referenced in the context of the P6 architecture?
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When is an instruction issued in Tomasulo’s algorithm?
When is an instruction issued in Tomasulo’s algorithm?
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In which stage of Tomasulo's algorithm is the instruction's result written back to the destination register?
In which stage of Tomasulo's algorithm is the instruction's result written back to the destination register?
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What role does the Re-order Buffer (ROB) serve in a processor's architecture?
What role does the Re-order Buffer (ROB) serve in a processor's architecture?
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What is the primary benefit of dynamic branch prediction over static branch prediction?
What is the primary benefit of dynamic branch prediction over static branch prediction?
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Which statement accurately describes the commit stage in Tomasulo’s algorithm?
Which statement accurately describes the commit stage in Tomasulo’s algorithm?
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What is a major drawback of static branch prediction?
What is a major drawback of static branch prediction?
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Which of the following correctly describes the saturating counters used in dynamic branch prediction?
Which of the following correctly describes the saturating counters used in dynamic branch prediction?
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What occurs when a branch is taken during pipeline execution?
What occurs when a branch is taken during pipeline execution?
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In the context of Netburst architecture, what advantage does scheduling all functional units in advance provide?
In the context of Netburst architecture, what advantage does scheduling all functional units in advance provide?
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How does the branch history table (BHT) aid in dynamic branch prediction?
How does the branch history table (BHT) aid in dynamic branch prediction?
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What type of branches does static prediction identify as always taken?
What type of branches does static prediction identify as always taken?
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What is a likely consequence of a branch prediction mismatch?
What is a likely consequence of a branch prediction mismatch?
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What does a two-level adaptive predictor utilize to make predictions?
What does a two-level adaptive predictor utilize to make predictions?
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What is the main drawback of a global branch predictor?
What is the main drawback of a global branch predictor?
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Which predictors concatenate local and global branch histories?
Which predictors concatenate local and global branch histories?
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In a gshare predictor, how is the index in the prediction history table determined?
In a gshare predictor, how is the index in the prediction history table determined?
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What is the function of local branch prediction?
What is the function of local branch prediction?
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What type of predictor is used to detect loops in conditional jumps?
What type of predictor is used to detect loops in conditional jumps?
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What method does the Agree predictor utilize?
What method does the Agree predictor utilize?
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What information does the global branch predictor primarily use?
What information does the global branch predictor primarily use?
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What is the primary purpose of the prediction history buffer?
What is the primary purpose of the prediction history buffer?
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What is the role of a pattern history table in branch prediction?
What is the role of a pattern history table in branch prediction?
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Which branch predictor type is characterized by individual history buffers?
Which branch predictor type is characterized by individual history buffers?
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Which architecture was noted for using local branch predictors with 4-bit history?
Which architecture was noted for using local branch predictors with 4-bit history?
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What is the influence of a two-bit counter in branch prediction?
What is the influence of a two-bit counter in branch prediction?
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What is one drawback of using a global branch predictor over a local branch predictor?
What is one drawback of using a global branch predictor over a local branch predictor?
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Study Notes
Computer Systems Structure - Central Processing Unit (CPU)
- The central processing unit (CPU) is a core component of computer systems.
Hazard Cases and Solutions
- Solutions for hazard cases in CPU pipelines involve techniques like scoreboard methods, Tomasulo's method, and branch prediction.
Scoreboard Method
- Used initially in the CDC 6600 computer (1966).
- Dynamically schedules instructions in a pipeline to avoid conflicts, enabling out-of-order execution if hardware is available, and no structural hazards.
- Logs data dependencies for each instruction.
- Releases instructions only when the scoreboard confirms no conflicts with previously issued, incomplete instructions.
- If an instruction stalls due to dependencies, the scoreboard monitors the pipeline to resolve those dependencies before continuing the stalled instruction.
- Instructions progress through four stages (Issue, Decode, Read Operands, Execution, Write result) before completion.
- Stages include operations like checking for structural and WAW hazards, and waiting for RAW hazards resolution.
- Scoreboard hardware has a similar cost to an FPU but could be more demanding on buses in modern processors.
- Important to note, this method does not handle forwarding.
- Stalls occur when required functional units are busy, affecting subsequent instructions.
Tomasulo's Algorithm
- Avoids structural hazards and resolves WAR and WAW hazards using register renaming and a Common Data Bus (CDB).
- Used first in IBM 360/91 computer (1969).
- Employs register renaming to create multiple copies of physical registers, minimizing dependencies.
- Real data dependencies cause no problems, unlike the limited number of registers causing a bottleneck.
- Data is placed on a CDB, and made available promptly, avoiding unnecessary delays in execution until the data is written into the destination register.
- Instructions proceed through issue, execute, write stages, carefully managing RAW dependencies and utilizing virtual values until real ones become available.
- Crucial to note this addresses issues not resolved by the scoreboard method.
Reservation Stations
- Buffers that acquire and store instruction operands for immediate availability.
- Reservation stations keep the data and result of an instruction.
- Points to registers (data is available) or other reservation stations containing necessary data before writing back to a register.
- Stores the result of an instruction execution and releases functional units once instruction execution completes.
- This release then makes results available for other reservation stations, avoiding delays.
Branch Prediction
- A method for mitigating control hazards caused by conditional jumps, by predicting the correct branch path.
- Static prediction is based on analyzing the branch instruction itself, to determine if it will take the branch or not. Common cases like procedure calls and unconditional jumps are analyzed to predict the decision.
- Dynamic prediction incorporates history of previous branch executions, to predict future behavior.
- Methods include next line prediction, and saturating counters.
Branch Prediction Methods (Dynamic)
- Next line predictor - Method stores the address of the next instruction(s) after the jump, along with the branch target address.
- Saturating counters - Use one or two bits to keep track of the decision taken in past executions. States such as Strongly not taken, weakly not taken, weakly taken, and strongly taken are used.
- Various prediction methods and modifications such as Two-level adaptive prediction, are described.
Branch Target Buffer (BTB)
- A dedicated structure containing target addresses for taken branches from past calculations, enabling faster future evaluation. -Contains jump instruction address, target address, and prediction state.
Tournament Predictor
- A powerful prediction method that combines local and global information using a selector to determine the ideal prediction based on a given branch.
Correlated Prediction - Overview
- This method combines aspects of local and global prediction, to improve accuracy.
- It considers a history table where each entry is assigned four predictors.
Misprediction Statistics/General
- Statistics about misprediction rates from simulations of the different architectures.
- Various configurations can be evaluated (number of entries, or bits per history table entry).
Commit Stage (Tomasulo's Algorithm)
- An additional stage in Tomasulo's algorithm, ROB (Reorder Buffer) assists in committing instructions in the correct order, even if their execution was out of order.
- Results are written to the ROB (Reorder Buffer) and not directly into the final destinations to allow for later reordering and avoiding pipeline stalls.
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Description
This quiz focuses on the central processing unit (CPU) in computer systems, particularly addressing the techniques used to solve hazard cases in CPU pipelines. Topics include the scoreboard method and various solutions for optimizing instruction scheduling in modern CPUs.
