Computer System Design Challenges

Study Notes

The Main Challenges

System complexity
Increasing performance
Stringent design requirements
Low cost and low power
Dependability: reliability, safety, and security
Testability and flexibility
Technology challenges for cost-efficient implementation
Deep submicron effects (e.g., cross-talk and soft errors)

Possible Solutions

Powerful design methodology and CAD tools
Advanced architecture (modularity)
Extensive design reuse
Programmable logic taxonomy

History of Programmable Logic

Simple Programmable Logic Devices (SPLDs)
PROM (Programmable Read-Only Memory) structure:
- One programmable plane
- Finite combination of ANDs/ORs
- Lower fuse count
- AND plane is fixed, and OR plane is programmable

Programmable Logic Devices (PLDs)

PLD programming languages:
- Many PAL programming devices accept input in a standard file format, commonly referred to as 'JEDEC files'
- The languages used as source code for logic compilers are called hardware description languages (HDLs)
- PALASM, ABEL, and CUPL are frequently used for low-complexity devices
- Verilog and VHDL are popular higher-level description languages for more complex devices
PROM structure:
- Binary to gray code converter

Programmable Array Logic (PAL)

OR array is fixed
AND array is programmable
PAL realization of function:
- fα (A, B, C, D) = ABD + BCD + ABCD
- fβ (A, B, C, D) = AB + BCD
- fγ (A, B, C, D) = ABD + BCD + ABCD

PLD Programming Technologies

Fuses:
- A fusible-link technology is required to implement links as fuses
- All links are initially active and must be selectively removed
- One-time programmable — unless redundant fuses or devices can be switched in to provide twice-programmable devices
Flash cells:
- Higher density but slower to erase and write

Field-Programmable Gate Arrays (FPGAs)

Typical complexity: 92,000,000,000 transistors in 2021 by Xilinx
Basic FPGA operation:
- Writing configuration memory defines system function
- Input/Output Cells
- Logic in PLBs
- Connections between PLBs and I/O cells
Can change at anytime, even while the system function is in operation

FPGA Resources

Ranges of resources:
- Small FPGA: 256 PLBs, 1 LUTs and flip-flops per PLB, etc.
- Large FPGA: 25,920 PLBs, 8 LUTs and flip-flops per PLB, etc.
Programmable logic cells:
- Xilinx: "configurable logic block" (CLB) contains SRAM lookup tables (LUTs) to implement combinational logic, D flip-flops, and multiplexers to establish paths in the CLB
- Actel: multiplexers implement logic
- Altera: similar to Xilinx CLB

Multiplexer-Based Logic Blocks in FPGAs

Virtex and Spartan 2:
- Array of 96 to 6,144 PLBs
- 4 LUTs/RAMs (4-input) and 4 FF/latches
- 4 to 32 4K-bit dual-port RAMs
Virtex II and Virtex II Pro:
- Array of 352 to 11,204 PLBs
- 8 LUTs/RAMs (4-input) and 8 FF/latches
- 12 to 444 18K-bit dual-port RAMs
- 12 to 444 18x18-bit multipliers
- 0 to 2 PowerPC processor cores
Virtex 4:
- Array of 1,536 to 22,272 PLBs
- 4 LUTs/RAMs (4-input) and 4 LUTs (4-input) and 8 FF/latches
- 48 to 552 18K-bit dual-port RAMs
- 32 to 512 DSP cores

Xilinx: Basic CLB Architecture

Look-up Table (LUT) implements truth table
Memory elements:
- Flip-flop/latch
- Some FPGAs - LUTs can also implement small RAMs
Carry and control logic implements fast adders/subtractors

Combinational Logic Functions

Gates are combined to create complex circuits
Multiplexer example:
- If S = 0, Z = A
- If S = 1, Z = B
- Very common digital circuit
- Heavily used in FPGAs

Look-up Tables

Recall multiplexer example
Configuration memory holds outputs for truth table
Internal signals connect to control signals of multiplexers to select value of truth table for any given input value

Look-up Table-Based RAMs

Functions of more variables than LUT inputs
f(a1, a0, b1, b0) = a1f(1, a0, b1, b0) + a1’f(0, a0, b1, b0)

A Simple CLB

Two 3-input LUTs
Can implement any 4-input combinational logic function
1 flip-flop
Programmable: active levels, clock edge, set/reset, and 22 configuration memory bits

Using Lookup-Table (LUT) Programmable Logic

Functions of more variables than the number of LUT inputs
Shannon's Expansion Theorem (partition into smaller functions): Z(a, b, c, d, e, f) = a’Z(0, b, c, d, e, f) + aZ(1, b, c, d, e, f)

Synchronous Sequential Circuit

CLB as a full adder

Interconnect Network

Programmable Interconnect Points (PIPs)
Also known as Configurable Interconnect Points (CIPs)
Transmission gate connects to 2 wire segments
Controlled by configuration memory bit

Xilinx Interconnect Structures

Break-point PIP
Cross-point PIP
Multiplexer PIP
Compound cross-point PIP
Switch box

Input/Output Cells

Bi-directional buffers
Flip-flops/latches for improved timing
Pull-up/down resistors
Programmable I/O voltage and current levels

Clock Regions

Logic resources
Logic resources
Clock region
Clock routing
Center clock
Column(s)

Description

This quiz covers the main challenges faced in computer system design, including system complexity, performance, and cost considerations. It also touches on technology challenges and deep submicron effects.

Computer System Design Challenges

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Questions and Answers

What is the main advantage of Flash cells?

What is the function of a Look-up Table (LUT) in an FPGA?

What is the role of Programmable Interconnect Points (PIPs) in an FPGA?

What is the function of a Multiplexer PIP in an FPGA?

What is the purpose of a Break-point PIP in an FPGA?

What is the main advantage of using an FPGA compared to a PAL or PROM?

What is the function of a clock region in an FPGA?

What is the purpose of a RAM core in an FPGA?

What is the function of a DSP core in an FPGA?

What is the main advantage of using a CLB in an FPGA?