Computer Structure and Function

Computer Structure

• The computer structure consists of four main components: Main Memory, I/O devices, System BUS, and CPU
• CPU consists of ALU, Internal BUS, Registers, and Control Unit
• Control Unit controls the operation of the CPU and hence the computer
• Arithmetic and logic unit (ALU) performs the computer's data processing functions
• Registers provide storage internal to the CPU
• CPU interconnection provides communication among the control unit, ALU, and registers

Creating a Program

• A program is a sequence of steps
• Instruction Interpreter: a device that accepts instruction codes and turns them into control signals for the arithmetic and logic hardware
• Encoding Instructions: unique binary patterns identify the operation to be performed

CPU Operations

• Fetch Cycle: Processor fetches an instruction from memory location pointed to by the Program Counter (PC)
• PC holds the address of the next instruction to fetch
• Instruction loaded into the Instruction Register (IR)
• Processor interprets the instruction and performs required actions

Execution Cycle

• Execute Cycle: the processor performs the required actions based on the instruction
• Processor-memory: data transfer between CPU and main memory
• Processor-I/O: data transfer between CPU and I/O module
• Data processing: some arithmetic or logical operation on data
• Control: alteration of sequence of operations, e.g., jump

Interrupts

• Types of Interrupts:
  • Program: "illegal instructions" (arithmetic overflow, divide by zero, or memory handling error)
  • Timer: "processor can perform some time-scheduled task"
  • I/O: "generated by an I/O controller to request service from the processor" (e.g., keyboard, mouse, NIC, disk drive)
  • Hardware failure: "signifies some error condition with the hardware"

Instruction Cycle

• Calculate Address Instruction
• Instruction Fetch
• Decode instruction
• Calculate operand address
• Fetch operand
• Operand operation
• Operand address calculation
• Operand store
• Check interrupt

I/O Modules

• Transfer data back and forth with the device as if it were memory
• Alternatively, the processor can grant the I/O module permission to write directly to memory - Direct Memory Access (DMA)
• Interrupt occurs when DMA is complete

Registers

• Program Counter (PC): holds the address of the next instruction
• Memory Address Register (MAR): connected to the address bus, specific address for read and write operation
• Memory Buffer Register (MBR): connected to the data bus, specific data to read or write last data
• Instruction Register (IR): holds the instruction after fetch

Micro-operations

• Transfer data between registers
• Transfer data from register to external
• Transfer data from external to register
• Perform arithmetic or logical operations

Flowchart of Instruction Cycle

• Fetch Cycle:
  • T1: MAR <- PC
  • T2: MBR <- Memory[PC]
  • T3: IR <- MBR
• Indirect Cycle:
  • T1: MAR <- IR
  • T2: MBR <- Memory
  • T3: IR <- MBR
• Interrupt Cycle:
  • T1: MBR <- PC
  • T2: MAR <- Saved Address
  • T2: Memory <- MBR

Addressing Modes

• Direct Addressing (MODE 0): the instruction code specifies the address of an operand
• Indirect Addressing (MODE 1): the bits of the second part of the instruction designate an address of a memory word in which the address of the operand is found