Computer Organization: Processors

<p>Reduced Instruction Set Computers</p> Signup and view all the answers

<p>To control all system operations based on high and low voltage signals</p> Signup and view all the answers

<p>Clock rate or frequency</p> Signup and view all the answers

<p>CISC</p> Signup and view all the answers

<p>Million cycles per second</p> Signup and view all the answers

<p>RISC</p> Signup and view all the answers

<p>Clock period (T)</p> Signup and view all the answers

<p>CPU</p> Signup and view all the answers

<p>CPU</p> Signup and view all the answers

<p>Serving as a hardware circuit board</p> Signup and view all the answers

<p>Motherboard</p> Signup and view all the answers

<p>$Memory$</p> Signup and view all the answers

<p>$Control$ $unit$ $in$ $CPU$</p> Signup and view all the answers

<p>CPU</p> Signup and view all the answers

<p>Monitor</p> Signup and view all the answers

<p>Motherboard</p> Signup and view all the answers

<p>Motherboard or Printed Circuit Board (PCB)</p> Signup and view all the answers

<p>Processor (CPU), main memory, I/O devices, and interconnected wires (Bus)</p> Signup and view all the answers

<p>Determining operations and instruction execution</p> Signup and view all the answers

<p>Holds the address of the main memory location</p> Signup and view all the answers

<p>ALU (Arithmetic Logic Unit)</p> Signup and view all the answers

<p>Specific types of data such as program counter and instruction currently being executed</p> Signup and view all the answers

<p>Bits reflecting the outcome of the last arithmetic and logic operation performed by the CPU</p> Signup and view all the answers

<p>The major functional units of a basic computer system are the motherboard, CPU, datapath, registers, and instruction cycle.</p> Signup and view all the answers

<p>The data processing takes place in the CPU.</p> Signup and view all the answers

<p>The control unit in the CPU retrieves the instructions, one by one, from the program stored in the memory and manipulates the data to execute the operation specified by the instruction.</p> Signup and view all the answers

<p>A motherboard is a hardware circuit board made of plastic and silicon, and it serves as a hub of a computer system.</p> Signup and view all the answers

<p>A digital computer can perform arithmetic computations, manipulate strings of alphabetic characters, and be programmed to make decisions based on internal and external conditions.</p> Signup and view all the answers

<p>The program and data prepared by the user are transferred into memory by means of an input device such as a keyboard.</p> Signup and view all the answers

<p>The two main components of the CPU are the Control Unit (CU) and Datapath. The Control Unit is responsible for determining operations and the Datapath is responsible for data processing.</p> Signup and view all the answers

<p>The Memory Address Register (MAR) holds the address of the main memory location, while the Memory Data Register (MDR) holds the data to be read from or written into main memory.</p> Signup and view all the answers

<p>Special-purpose registers store specific types of data such as the program counter and the instruction currently being executed.</p> Signup and view all the answers

<p>The Flag register contains bits reflecting the outcome of the last arithmetic and logic operation performed by the CPU.</p> Signup and view all the answers

<p>The main components of a digital computer are the processor (CPU), main memory, I/O devices, and interconnected wires called Bus.</p> Signup and view all the answers

<p>Registers inside the CPU store intermediate results, data needed for instruction execution, and specific types of data such as the program counter and the instruction currently being executed.</p> Signup and view all the answers

<p>The system clock is used to synchronize all components on the motherboard, ensuring that all computer components do their work only when the clock is high, never when it's low.</p> Signup and view all the answers

<p>The length of one clock cycle measured in units of time is called the clock period (T), and the inverse of the period (1/T) is called the clock rate or the clock frequency (F), which gives the number of cycles per second and is measured in Hertz (Hz).</p> Signup and view all the answers

<p>RISC processors aim to reduce the number of clock cycles needed to execute an instruction by using simple machine instructions that take only one clock cycle to execute, while CISC processors aim to decrease the number of machine instructions per program by using complex instructions that may require more than one clock cycle to be performed.</p> Signup and view all the answers

<p>Suppose the operation A=A+5 needs to be performed. On a CISC processor, this can be done by a single complex machine instruction, while on a RISC processor, it requires three instructions: Load R0, A; Add R0, 5; and Store A, R0. The CISC approach reduces the program size to one machine instruction but may take more than one clock cycle to execute, while the RISC approach increases the program size to three instructions, each taking only one clock cycle to execute.</p> Signup and view all the answers

<p>CISC processors require complex hardware that is capable of performing many simple tasks in one complex machine instruction in order to reduce the number of machine instructions per program.</p> Signup and view all the answers

<p>The most important thing to consider when designing a processor is the program execution speed, which is determined by the time needed to execute a program, the number of instructions per program, the number of processor cycles needed to perform the instruction, and the time of the processor cycle (period).</p> Signup and view all the answers

<p>The clock rate or frequency of a computer system is measured in Hertz (Hz), with 1 MHz being equivalent to 1 million cycles per second.</p> Signup and view all the answers

<p>The system clock is used to synchronize all components on the motherboard, ensuring that all computer components do their work only when the clock is high, never when it's low.</p> Signup and view all the answers

<p>Array Processor uses a large number of identical processors to perform the same instruction on different operands, while Multiprocessors have independent CPUs sharing a common memory.</p> Signup and view all the answers

<p>Multicomputer</p> Signup and view all the answers

<p>By reading and writing messages into the shared main memory.</p> Signup and view all the answers

<p>MP-1216 with a maximum of 16384 processors each are 4-bit</p> Signup and view all the answers

<p>Independent CPUs sharing a common memory.</p> Signup and view all the answers

<p>$Array$ $Processor$</p> Signup and view all the answers

<p>CPUs communicate by passing messages to each other like email.</p> Signup and view all the answers

<p>CPUs communicate by reading and writing messages into shared main memory.</p> Signup and view all the answers

<p>Multiprocessors</p> Signup and view all the answers

<p>Sequential execution ensures no instruction starts until the previous is completed, while pipeline execution allows partial overlapping of instruction execution</p> Signup and view all the answers

<p>Each stage completes its operation in one clock cycle</p> Signup and view all the answers

<p>When one instruction depends on the result of a previous instruction</p> Signup and view all the answers

<p>The time needed for the pipeline to become full</p> Signup and view all the answers

<p>Pentium 4</p> Signup and view all the answers

<p>The time needed by the CPU to finish executing a single instruction</p> Signup and view all the answers

<p>Executing multiple instructions at the same time</p> Signup and view all the answers

<p>Processor Level Parallel processing</p> Signup and view all the answers

<p>Use of multiple pipelines or execution units to process more than one instruction at a time</p> Signup and view all the answers

<p>Partial overlapping of the execution of two instructions in pipeline execution</p> Signup and view all the answers

<p>Reducing the number of clock cycles needed to execute an instruction</p> Signup and view all the answers

<p>Superscalar architecture</p> Signup and view all the answers

<p>Instruction decoding and executing</p> Signup and view all the answers

<p>Partial overlapping of the execution of two instructions</p> Signup and view all the answers

<p>Using multiple CPUs to solve a single problem</p> Signup and view all the answers

<p>To allow the processing of more than one instruction at a time</p> Signup and view all the answers

<p>Partial overlapping of the execution of two instructions</p> Signup and view all the answers

<p>To make a single CPU perform several instructions at the same time</p> Signup and view all the answers

<p>To store status information about the state of the processor</p> Signup and view all the answers

<p>Execute</p> Signup and view all the answers

<p>The duration of one clock cycle, determining the speed of the processor</p> Signup and view all the answers

<p>Arithmetic Logic Unit (ALU)</p> Signup and view all the answers

<ol> <li>Array Processor: Uses identical processors to perform the same instruction on different data sets. 2) Multiprocessors: Independent CPUs sharing a common memory with their own local memory. 3) Multicomputer: Standalone interconnected computers that appear as a single system to the end user.</li> </ol> Signup and view all the answers

<p>Examples include ILLIAC-IV with 64-bit processors, CM-2 machine with up to 65536 processors, and MP-1216 with a maximum of 16384 processors.</p> Signup and view all the answers

<p>CPUs communicate with each other by reading and writing messages into the shared main memory.</p> Signup and view all the answers

<p>Standalone interconnected computers that appear as a single system to the end user, where CPUs communicate by passing messages to each other like email.</p> Signup and view all the answers

<p>Data dependency occurs when one instruction depends on the result of a previous instruction. For example, if instruction 2 requires the result of instruction 1 before it can proceed, there is a data dependency between these two instructions.</p> Signup and view all the answers

<p>Pipeline setup time is the time needed for the pipeline to become full, allowing continuous and efficient operation. It signifies the delay before the pipeline can achieve maximum throughput and start producing results.</p> Signup and view all the answers

<p>Constraints on instruction level parallel processing include data dependency and resource conflict. Data dependency introduces stalls in the pipeline, while resource conflict leads to competition for the same hardware units, both impacting the processor's ability to achieve maximum parallelism and performance.</p> Signup and view all the answers

<p>The two types of parallel processing discussed in the text are Instruction Level Parallel Processing (Pipelining) and Processor Level Parallel Processing. Instruction Level Parallel Processing involves making a single CPU perform several instructions at the same time, while Processor Level Parallel Processing involves using multiple CPUs to solve a single problem.</p> Signup and view all the answers

<p>The five main steps involved in the program execution process of Instruction Level Parallel Processing (ILP) are: 1. Fetch Instruction, 2. Decode Instruction, 3. Fetch operand, 4. Execute, 5. Store Results. Each step involves retrieving and processing specific information or data related to the instruction being executed.</p> Signup and view all the answers

<p>In sequential execution, no instruction can start executing until the previous instruction is completed. In pipeline execution, there is partial overlapping of the execution of two instructions, allowing for some parallelism. Superscalar architecture refers to the use of multiple pipelines or a single pipeline with multiple execution units to process more than one instruction at a time.</p> Signup and view all the answers

<p>Transferring data between devices</p> Signup and view all the answers

<p>Data lines, Address Lines, Control Lines</p> Signup and view all the answers

<p>A scheme to avoid conflicts when multiple devices want to use the bus simultaneously</p> Signup and view all the answers

<p>Deciding which device will be allowed to use the bus</p> Signup and view all the answers

<p>Centralized Arbitration and Distributed Arbitration</p> Signup and view all the answers

<p>To have a central control device decide which device will be allowed to use the bus</p> Signup and view all the answers

<p>Address information for memory and I/O devices</p> Signup and view all the answers

<p>Carrying commands from CPU to Memory and I/Os</p> Signup and view all the answers

<p>Devices resolve conflicts among themselves without a central arbiter</p> Signup and view all the answers

<p>The arbiter issues a grant signal to the highest priority request line only</p> Signup and view all the answers

<p>Priorities are fixed and arbitration time increases as the number of devices increases</p> Signup and view all the answers

<p>Peripheral Components Interconnect bus with each device having its own bus request and grant lines</p> Signup and view all the answers

<p>Distributed arbitration without a central arbiter</p> Signup and view all the answers

<p>Distributed arbitration without a central arbiter</p> Signup and view all the answers

<p>Multiple shared bus request with different priority levels using daisy chaining</p> Signup and view all the answers