Computer Logic Gates and Architecture Quiz
40 Questions
0 Views

Choose a study mode

Play Quiz
Study Flashcards
Spaced Repetition
Chat to lesson

Podcast

Play an AI-generated podcast conversation about this lesson

Questions and Answers

What gate is represented by the truth table where A op B outputs 1 when either A is 1 or B is 1 but not both?

  • XOR Gate (correct)
  • NAND Gate
  • OR Gate
  • AND Gate

    • Which gate will output a 0 only if both A and B are 1?

  • NOR Gate
  • AND Gate (correct)
  • OR Gate
  • XOR Gate

    • For the truth table that outputs 1 only when at least one input is 0, which gate is being described?

  • OR Gate
  • AND Gate
  • NAND Gate (correct)
  • NOR Gate

    • Which gate's truth table will result in a 1 only when both A and B are 0?

    <p>NOR Gate</p> Signup and view all the answers

    What is the output of a NAND gate when both inputs are 1?

    <p>0</p> Signup and view all the answers

    Which logic gate will yield a 1 when both inputs are the same?

    <p>XNOR Gate</p> Signup and view all the answers

    If a logic gate has a truth table showing an output of 0 only when both A and B are true, what type of gate is it?

    <p>AND Gate</p> Signup and view all the answers

    Which gate produces a high output (1) when at least one of its inputs is high (1)?

    <p>OR Gate</p> Signup and view all the answers

    Which method involves the CPU checking a status register before copying data to or from a peripheral device?

    <p>Programmed I/O</p> Signup and view all the answers

    What is one disadvantage of port mapped I/O?

    <p>Limited number of I/O ports</p> Signup and view all the answers

    What is one disadvantage of memory mapped I/O?

    <p>Requires more complex CPU architecture</p> Signup and view all the answers

    Which addressing mode is used by the instruction LDA #$0D?

    <p>Immediate Addressing</p> Signup and view all the answers

    What is the value of register A after executing the instruction LDA #$0D?

    <p>$0D</p> Signup and view all the answers

    Which addressing mode does the instruction LDY $0D use?

    <p>Direct Addressing</p> Signup and view all the answers

    What is the value of register Y after executing the instruction LDY $(000F), X?

    <p>$OD</p> Signup and view all the answers

    Which flag (P) indicates a negative value in the 6502 CPU architecture?

    <p>N</p> Signup and view all the answers

    What is the objective in the game Centipede?

    <p>Reach square 8 in the fewest moves possible.</p> Signup and view all the answers

    How does the game Centipede handle overshooting?

    <p>Players stay at the same square.</p> Signup and view all the answers

    What does the output bit (P) of a 3-bit parity generator ensure?

    <p>The number of 1s output is always odd.</p> Signup and view all the answers

    Which of the following is NOT a function of the Control Unit?

    <p>Executing arithmetic operations.</p> Signup and view all the answers

    What is one of the key concepts of the von Neumann Architecture?

    <p>Single bus architecture.</p> Signup and view all the answers

    In Frequency Modulation (FM) encoding, how is a 1 represented?

    <p>By a higher frequency signal.</p> Signup and view all the answers

    What are the concentric rings on a hard disk platter called?

    <p>Tracks.</p> Signup and view all the answers

    What part of a computer manages data transfer between peripherals and the CPU?

    <p>The direct memory access (DMA) controller.</p> Signup and view all the answers

    What is the term for the situation where multiple processes access the same memory location simultaneously and at least one is modifying it?

    <p>Race condition</p> Signup and view all the answers

    Which mechanism simplifies synchronization for programmers in high-level programming languages?

    <p>Semaphore</p> Signup and view all the answers

    Which conditions are necessary for a deadlock to occur?

    <p>Mutual exclusion, hold and wait, no preemption</p> Signup and view all the answers

    What is the component in the CPU responsible for translating logical addresses into physical addresses?

    <p>Memory Management Unit (MMU)</p> Signup and view all the answers

    What is the name for the situation where there is sufficient overall memory but no contiguous block is large enough to satisfy a request?

    <p>Fragmentation</p> Signup and view all the answers

    In a typical UNIX system, which two system calls are used to launch another program?

    <p>exec() and fork()</p> Signup and view all the answers

    What is the cache used to speed up page table access called?

    <p>TLB (Translation Lookaside Buffer)</p> Signup and view all the answers

    When accessing an invalid page, the resulting trap in the CPU is referred to as what?

    <p>Page fault</p> Signup and view all the answers

    What is the primary function of the Compare-And-Swap instruction (CAS)?

    <p>To ensure mutual exclusion in concurrent processes.</p> Signup and view all the answers

    Given a logical address space of 16 bytes and a page size of 4 bytes, how many pages can be created?

    <p>4 pages</p> Signup and view all the answers

    In a page table, what does the 'frame' represent?

    <p>The allocation of physical memory for a process.</p> Signup and view all the answers

    What can be inferred about the mappings in the page table if logical address 0111 is mapped to physical address 10111?

    <p>Page frame for logical address 0111 is F2</p> Signup and view all the answers

    How many page faults are expected when using the FIFO page replacement algorithm on the reference string given a memory of four physical frames?

    <p>6 page faults</p> Signup and view all the answers

    In a system that uses indexed allocation with 12 direct pointers and one indirect pointer, what does the indirect pointer allow?

    <p>Access to more data blocks beyond the fixed size.</p> Signup and view all the answers

    What is the maximum file size that can be supported by the system if each data block is 4096 bytes and the inode has 12 direct pointers and one indirect pointer?

    <p>52,224 bytes</p> Signup and view all the answers

    When using LRU page replacement on the same reference string, what is the expected number of page faults?

    <p>6 page faults</p> Signup and view all the answers

    Study Notes

    Logic Gates

    • OR Gate: Outputs a 1 if either input A or input B is 1, or both are 1
    • AND Gate: Outputs a 1 only if both input A and input B are 1.
    • XOR Gate: Outputs a 1 if either input A or input B is 1, but not both.
    • NOT Gate: Inverts the input signal, outputting a 1 if the input is 0 and a 0 if the input is 1.
    • NAND Gate: Outputs a 0 only if both input A and input B are 1, and outputs a 1 otherwise.

    Computer Architecture

    • CPU Busses: Address Bus, Data Bus, Control Bus
    • Control Unit Functions: Fetching instructions, decoding instructions, sequencing operations
    • Von Neumann Architecture Concepts: Instructions and data share the same memory space, sequential execution of instructions, single address space for both instructions and data.
    • RISC Architecture: Instruction per cycle, Register to register operations
    • CPU Operation Cycles: Fetch, Decode, Execute, Write Back

    Peripherals

    • Frequency Modulation (FM) Encoding: 0 is encoded as a low frequency signal, 1 is encoded as a high frequency signal.
    • Modified Frequency Modulation (MFM) Encoding: 0 is encoded as a transition in the middle of the bit period, 1 is encoded as a transition at the start of the bit period.
    • Concentric rings on a hard disk platter: Tracks
    • Wedge of a concentric ring: Sector
    • Device copying data from (or to) a peripheral device: Direct Memory Access (DMA) controller
    • Alternative method of data transfer where CPU copies data: Programmed I/O
    • Port mapped I/O Disadvantage: Limited address space and potential conflicts with peripheral addresses.
    • Memory mapped I/O Disadvantage: Additional memory space required for device addresses.

    Assembly Language

    • LDA #$0D addressing mode: Immediate addressing
    • Value of A after LDA #$0D: $0D
    • LDY $0D addressing mode: Zero page addressing
    • Value of Y after LDY $0D: $OD
    • LDY $(000F), X addressing mode: Indexed indirect addressing
    • Value of Y after LDY $(000F), X: $55
    • CLC before ADC: Used when you want to add two numbers without carrying over from a previous operation.
    • No CLC before ADC: If you want to maintain the carry flag from a previous addition.

    Operating System Concepts

    • Operating System (OS) manages: Resources of the computer like the CPU, memory, and peripherals, and provides services to users and applications.
    • Two spaces of the CPU: Kernel Space, User Space
    • Kernel Space: CPU has full privilege to access resources.
    • User Space: CPU cannot directly access resources without permission from the Kernel.
    • Processes issue requests to the Kernel: System calls
    • Three sections of a process memory layout: Text segment, Data segment, Stack segment
    • Process management data structure: Process Control Block (PCB)
    • Shared resources of a thread: Text Segment, Data Segment
    • Terminate a process: Signal
    • Terminated child process with a live parent process: Zombie
    • Multiple accesses to shared data: Race Condition
    • High-level synchronization construct: Semaphore
    • Deadlock conditions: Mutual exclusion, Hold and wait, No preemption, Circular wait.
    • CPU unit responsible for address translation: Memory Management Unit (MMU)
    • Insufficient contiguous memory: Fragmentation
    • UNIX system calls to launch another program: fork() and exec()
    • Page table cache in CPU: Translation Lookaside Buffer (TLB)
    • Trap occurring on access to invalid page: Page Fault
    • File system data retrieval/modification system calls: open(), read(), write(), close()
    • Delegating I/O tasks to a special-purpose processor: DMA (Direct Memory Access)
    • Kernel module that understands device hardware: Device Driver

    Semaphore Implementation

    // setup.This is guaranteed to be run exactly once, before anything else.void setup() {
  // YOUR CODE HERE
  init(s, 1); // Initialize semaphore with value 1 
}
  
int counter = 0;
void incrementCounter() {
  // YOUR CODE HERE
  wait(s); // Acquire the semaphore
  counter = counter + 1;
  signal(s); // Release the semaphore
}

void decrementCounter() {
  // YOUR CODE HERE
  wait(s); // Acquire the semaphore
  counter = counter - 1;
  signal(s); // Release the semaphore 
}

    Compare-And-Swap Instruction

    • CAS(o, a, n): Atomically compares the value of a memory location (o) with an expected value (a), and if they match, updates the memory location with a new value (n).

    Paging System

    • CPU*
    address P off f off
    0010 001 010
    1001 100 001
    0111 011 011
    • Page Table*
    page frame
    001 0101
    011 1011
    100 1110
    111 1101

    Page Replacement Algorithms

    • FIFO Page Replacement Algorithm: The page that has been in memory the longest is replaced. The sequence results in 11 page faults
    • LRU Page Replacement Algorithm: The least recently used page is replaced. The sequence results in 10 page faults.

    Indexed Allocation

    • The largest file that can be stored: 12 direct pointers * 4096 bytes + 4096 bytes * 1024 pointers = 4,194,304 bytes + 4,194,304 * 1024 bytes

    Studying That Suits You

    Use AI to generate personalized quizzes and flashcards to suit your learning preferences.

    Quiz Team

    Related Documents

    University of Otago COSC243 Computer Science Exam 2019 PDF

    Description

    Test your knowledge on logic gates, computer architecture, and peripheral concepts. This quiz covers the functions of various gates and the principles of CPU operations within different architectures, including Von Neumann and RISC. Get ready to challenge yourself and see how much you know about these fundamental computing concepts!

    More Like This

    Computer Number Systems and Logic Gates Quiz
    3 questions

    Computer Number Systems and Logic Gates Quiz

    FruitfulCyan avatar
    FruitfulCyan
    Types of Logic Gates Quiz
    10 questions

    Types of Logic Gates Quiz

    HumourousTaiga avatar
    HumourousTaiga
    Introduction to Logic Gates and Computer Systems
    12 questions

    Introduction to Logic Gates and Computer Systems

    SelfSatisfactionSanDiego avatar
    SelfSatisfactionSanDiego
    Computer Hardware Fundamentals Quiz
    48 questions

    Computer Hardware Fundamentals Quiz

    ArtisticBlackberryBush avatar
    ArtisticBlackberryBush
    Use Quizgecko on...
    Browser
    Open
    Browser
    Browser