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What gate is represented by the truth table where A op B outputs 1 when either A is 1 or B is 1 but not both?
Which gate will output a 0 only if both A and B are 1?
For the truth table that outputs 1 only when at least one input is 0, which gate is being described?
Which gate's truth table will result in a 1 only when both A and B are 0?
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What is the output of a NAND gate when both inputs are 1?
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Which logic gate will yield a 1 when both inputs are the same?
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If a logic gate has a truth table showing an output of 0 only when both A and B are true, what type of gate is it?
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Which gate produces a high output (1) when at least one of its inputs is high (1)?
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Which method involves the CPU checking a status register before copying data to or from a peripheral device?
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What is one disadvantage of port mapped I/O?
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What is one disadvantage of memory mapped I/O?
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Which addressing mode is used by the instruction LDA #$0D?
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What is the value of register A after executing the instruction LDA #$0D?
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Which addressing mode does the instruction LDY $0D use?
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What is the value of register Y after executing the instruction LDY $(000F), X?
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Which flag (P) indicates a negative value in the 6502 CPU architecture?
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What is the objective in the game Centipede?
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How does the game Centipede handle overshooting?
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What does the output bit (P) of a 3-bit parity generator ensure?
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Which of the following is NOT a function of the Control Unit?
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What is one of the key concepts of the von Neumann Architecture?
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In Frequency Modulation (FM) encoding, how is a 1 represented?
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What are the concentric rings on a hard disk platter called?
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What part of a computer manages data transfer between peripherals and the CPU?
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What is the term for the situation where multiple processes access the same memory location simultaneously and at least one is modifying it?
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Which mechanism simplifies synchronization for programmers in high-level programming languages?
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Which conditions are necessary for a deadlock to occur?
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What is the component in the CPU responsible for translating logical addresses into physical addresses?
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What is the name for the situation where there is sufficient overall memory but no contiguous block is large enough to satisfy a request?
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In a typical UNIX system, which two system calls are used to launch another program?
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What is the cache used to speed up page table access called?
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When accessing an invalid page, the resulting trap in the CPU is referred to as what?
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What is the primary function of the Compare-And-Swap instruction (CAS)?
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Given a logical address space of 16 bytes and a page size of 4 bytes, how many pages can be created?
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In a page table, what does the 'frame' represent?
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What can be inferred about the mappings in the page table if logical address 0111 is mapped to physical address 10111?
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How many page faults are expected when using the FIFO page replacement algorithm on the reference string given a memory of four physical frames?
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In a system that uses indexed allocation with 12 direct pointers and one indirect pointer, what does the indirect pointer allow?
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What is the maximum file size that can be supported by the system if each data block is 4096 bytes and the inode has 12 direct pointers and one indirect pointer?
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When using LRU page replacement on the same reference string, what is the expected number of page faults?
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Study Notes
Logic Gates
- OR Gate: Outputs a 1 if either input A or input B is 1, or both are 1
- AND Gate: Outputs a 1 only if both input A and input B are 1.
- XOR Gate: Outputs a 1 if either input A or input B is 1, but not both.
- NOT Gate: Inverts the input signal, outputting a 1 if the input is 0 and a 0 if the input is 1.
- NAND Gate: Outputs a 0 only if both input A and input B are 1, and outputs a 1 otherwise.
Computer Architecture
- CPU Busses: Address Bus, Data Bus, Control Bus
- Control Unit Functions: Fetching instructions, decoding instructions, sequencing operations
- Von Neumann Architecture Concepts: Instructions and data share the same memory space, sequential execution of instructions, single address space for both instructions and data.
- RISC Architecture: Instruction per cycle, Register to register operations
- CPU Operation Cycles: Fetch, Decode, Execute, Write Back
Peripherals
- Frequency Modulation (FM) Encoding: 0 is encoded as a low frequency signal, 1 is encoded as a high frequency signal.
- Modified Frequency Modulation (MFM) Encoding: 0 is encoded as a transition in the middle of the bit period, 1 is encoded as a transition at the start of the bit period.
- Concentric rings on a hard disk platter: Tracks
- Wedge of a concentric ring: Sector
- Device copying data from (or to) a peripheral device: Direct Memory Access (DMA) controller
- Alternative method of data transfer where CPU copies data: Programmed I/O
- Port mapped I/O Disadvantage: Limited address space and potential conflicts with peripheral addresses.
- Memory mapped I/O Disadvantage: Additional memory space required for device addresses.
Assembly Language
- LDA #$0D addressing mode: Immediate addressing
- Value of A after LDA #$0D: $0D
- LDY $0D addressing mode: Zero page addressing
- Value of Y after LDY $0D: $OD
- LDY $(000F), X addressing mode: Indexed indirect addressing
- Value of Y after LDY $(000F), X: $55
- CLC before ADC: Used when you want to add two numbers without carrying over from a previous operation.
- No CLC before ADC: If you want to maintain the carry flag from a previous addition.
Operating System Concepts
- Operating System (OS) manages: Resources of the computer like the CPU, memory, and peripherals, and provides services to users and applications.
- Two spaces of the CPU: Kernel Space, User Space
- Kernel Space: CPU has full privilege to access resources.
- User Space: CPU cannot directly access resources without permission from the Kernel.
- Processes issue requests to the Kernel: System calls
- Three sections of a process memory layout: Text segment, Data segment, Stack segment
- Process management data structure: Process Control Block (PCB)
- Shared resources of a thread: Text Segment, Data Segment
- Terminate a process: Signal
- Terminated child process with a live parent process: Zombie
- Multiple accesses to shared data: Race Condition
- High-level synchronization construct: Semaphore
- Deadlock conditions: Mutual exclusion, Hold and wait, No preemption, Circular wait.
- CPU unit responsible for address translation: Memory Management Unit (MMU)
- Insufficient contiguous memory: Fragmentation
- UNIX system calls to launch another program: fork() and exec()
- Page table cache in CPU: Translation Lookaside Buffer (TLB)
- Trap occurring on access to invalid page: Page Fault
- File system data retrieval/modification system calls: open(), read(), write(), close()
- Delegating I/O tasks to a special-purpose processor: DMA (Direct Memory Access)
- Kernel module that understands device hardware: Device Driver
Semaphore Implementation
// setup.This is guaranteed to be run exactly once, before anything else.void setup() {
// YOUR CODE HERE
init(s, 1); // Initialize semaphore with value 1
}
int counter = 0;
void incrementCounter() {
// YOUR CODE HERE
wait(s); // Acquire the semaphore
counter = counter + 1;
signal(s); // Release the semaphore
}
void decrementCounter() {
// YOUR CODE HERE
wait(s); // Acquire the semaphore
counter = counter - 1;
signal(s); // Release the semaphore
}
Compare-And-Swap Instruction
- CAS(o, a, n): Atomically compares the value of a memory location (o) with an expected value (a), and if they match, updates the memory location with a new value (n).
Paging System
- CPU*
| address | P off | f off |
|---|---|---|
| 0010 | 001 | 010 |
| 1001 | 100 | 001 |
| 0111 | 011 | 011 |
- Page Table*
| page | frame |
|---|---|
| 001 | 0101 |
| 011 | 1011 |
| 100 | 1110 |
| 111 | 1101 |
Page Replacement Algorithms
- FIFO Page Replacement Algorithm: The page that has been in memory the longest is replaced. The sequence results in 11 page faults
- LRU Page Replacement Algorithm: The least recently used page is replaced. The sequence results in 10 page faults.
Indexed Allocation
- The largest file that can be stored: 12 direct pointers * 4096 bytes + 4096 bytes * 1024 pointers = 4,194,304 bytes + 4,194,304 * 1024 bytes
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Description
Test your knowledge on logic gates, computer architecture, and peripheral concepts. This quiz covers the functions of various gates and the principles of CPU operations within different architectures, including Von Neumann and RISC. Get ready to challenge yourself and see how much you know about these fundamental computing concepts!
