Computer Architecture Quiz

<p>Data in cache is more recent than in main memory. (D)</p> Signup and view all the answers

<p>Current Instruction Register (CIR) (B)</p> Signup and view all the answers

<p>When minimizing latency is the highest priority. (C)</p> Signup and view all the answers

<p>Running basic text editing tasks (A)</p> Signup and view all the answers

<p>It has a smaller set of simple instructions for faster execution. (D)</p> Signup and view all the answers

<p>The instructions, registers, and data memory formats. (B)</p> Signup and view all the answers

<p>It offers a rich set of complex instructions for ease of coding. (D)</p> Signup and view all the answers

<p>Holds temporary results of arithmetic and logic operations (B)</p> Signup and view all the answers

<p>Program Counter (PC) (D)</p> Signup and view all the answers

<p>Stores the data fetched from or being sent to memory (D)</p> Signup and view all the answers

<p>Instruction Buffer Register (IBR) (D)</p> Signup and view all the answers

<p>Both data and addresses (D)</p> Signup and view all the answers

<p>Keeps track of the call stack in use (A)</p> Signup and view all the answers

<p>Current Instruction Register (CIR) (C)</p> Signup and view all the answers

<p>By containing a displacement relative to a base address (D)</p> Signup and view all the answers

<p>Indicates whether there are bits that need to be carried to the next digit (C)</p> Signup and view all the answers

<p>OR Gate (B)</p> Signup and view all the answers

<p>To continue addition in subsequent bit calculations (B)</p> Signup and view all the answers

<p>Inverts the input value (D)</p> Signup and view all the answers

<p>To select a single output from multiple inputs based on control signals (D)</p> Signup and view all the answers

<p>Used for quick access and transfer of data currently in use (B)</p> Signup and view all the answers

<p>They have a limited number and low memory size (C)</p> Signup and view all the answers

<p>Bitwise manipulation of binary numbers (D)</p> Signup and view all the answers

<p>Multiple execution units for different operation types (D)</p> Signup and view all the answers

<p>Dividing tasks into smaller subtasks that run concurrently (D)</p> Signup and view all the answers

<p>Task Parallelism (B)</p> Signup and view all the answers

<p>Dynamic coordination of tasks among peers (C)</p> Signup and view all the answers

<p>Simultaneous execution of multiple tasks by a single CPU (A)</p> Signup and view all the answers

<p>Enhanced performance through parallel execution (D)</p> Signup and view all the answers

<p>Performs the same operation on multiple data points simultaneously (A)</p> Signup and view all the answers

<p>Scientific simulations (B)</p> Signup and view all the answers

<p>CPI (D)</p> Signup and view all the answers

<p>2 billion (D)</p> Signup and view all the answers

<p>Compile (B)</p> Signup and view all the answers

<p>1.5 milliseconds (C)</p> Signup and view all the answers

<p>By executing multiple instructions simultaneously (D)</p> Signup and view all the answers

<p>1.0 seconds (B)</p> Signup and view all the answers

<p>Ability to execute more than one instruction per clock cycle (B)</p> Signup and view all the answers

<p>3 million (A)</p> Signup and view all the answers

<p>Execution Time (B)</p> Signup and view all the answers

The Program Counter (PC) holds the address of the next instruction to be fetched from memory. It's like a pointer that tells the CPU where to find the next instruction in the program.

The Memory Address Register (MAR) temporarily stores the address of the memory location to be accessed. It acts as a buffer between the PC and the memory system, ensuring the correct data is fetched.

The Memory Buffer Register (MBR) holds the data being transferred between the CPU and memory. It works as a temporary storage for data being read from or written to memory.

The Current Instruction Register (CIR) holds the instruction that is currently being executed by the CPU. It breaks down the fetched instruction into its opcode and operand parts.

The Accumulator (AC) is a special register that stores intermediate results during arithmetic and logic operations. It acts like a scratchpad for the CPU, holding temporary calculations.

The carry bit that results from a mathematical operation, like addition or subtraction.

A circuit that can perform a variety of logic operations based on an input signal.

Building a complex ALU by starting with simple 1-bit ALUs and combining them.

A basic logic gate that outputs a '1' only when both inputs are '1'.

A basic logic gate that outputs a '1' if at least one of the inputs is '1'.

A logic gate that outputs a '1' if the inputs are different, and outputs a '0' if they're the same.

A circuit that selects an output based on a control signal.

A special circuit used in ALU's that adds two numbers and a carry input, outputting the sum and a carry output.

The total number of CPU clock cycles required to execute a program. It's calculated by multiplying the number of instructions in the program by the average number of clock cycles per instruction (CPI).

The average number of clock cycles required to execute a single instruction. It's a measure of how efficient a CPU is at executing instructions.

The speed at which the CPU operates. It's measured in Hertz (Hz) and represents the number of clock cycles per second.

The time it takes for the CPU to complete a program or task. It's measured in seconds or milliseconds.

A technique that increases CPU performance by executing multiple instructions simultaneously. It breaks down the execution of an instruction into stages, like fetch, decode, execute, memory, and write-back, and overlaps these stages for different instructions.

A CPU architecture that utilizes multiple execution units to execute multiple instructions concurrently within a single clock cycle. This enables faster processing by performing several operations in parallel.

The unit of time that represents the time interval between two consecutive clock cycles.

A special memory location that holds the location (address) of the next instruction to be executed in the program.

A register that temporarily stores the instruction that's currently being processed by the CPU.

A register that holds the data being fetched from or sent to memory by the CPU.

A specialized register that keeps track of the current location in memory where data will be fetched from or stored to.

A general-purpose register that serves as a temporary holding space for mathematical and logical calculations.

A register used to store intermediate values during calculations, function arguments, return values, and data addresses.

A register that keeps track of the locations of function calls in a memory stack. It's used for managing function calls and returns.

A register that holds an index value used to calculate an address by adding the index value to the base address. It's useful for accessing data in arrays or lists.

A cache organization where each memory block can be stored in one of a specific set of cache locations. The number of locations within the set determines the way (e.g., 2-way, 4-way).

A cache write policy where data is written to both cache and main memory simultaneously. This ensures data consistency but can increase latency due to frequent writes.

A cache write policy where data is initially written only to the cache and later updated in main memory as needed. This improves efficiency but risks data inconsistency if not carefully managed.

A flag that indicates whether data in cache has been modified. If 'dirty', the cache version is newer than main memory.

Modern CPUs are capable of handling complex workloads like AI computations, multimedia processing, software development, and information systems.

A technique where multiple processing units work together to execute instructions simultaneously, leading to faster program execution.

A method of dividing tasks into smaller, independent subtasks that can be executed concurrently on multiple processors. This allows for faster task completion.

A type of parallel processing where the same operation is performed on different sets of data simultaneously, using multiple processors.

A type of parallel processing where different tasks are distributed across multiple processors, allowing each core to work independently on a specific task.

A design that allows a single instruction to operate on multiple data elements simultaneously. This is common in graphics processing units (GPUs) for high-performance tasks like image processing.

The use of multiple CPU cores to execute multiple processes or threads concurrently. Each core can handle a separate task, enabling true parallel execution.

A type of multiprocessing where all cores share the same memory and operate as equals, dynamically coordinating tasks amongst themselves.