Computer Architecture Quiz

The study of how computers are designed, organized, and work. It covers the interaction between hardware and software.

The central processing unit (CPU) is the brain of a computer, responsible for executing instructions.

Memory is the temporary storage space for instructions and data being used by a program.

Input/Output units (I/O) allow the computer to interact with the outside world, like keyboards, monitors, and hard drives.

John von Neumann's architectural model, introduced in the 1940s, is a cornerstone principle in computer design. It proposes that a computer should have a single address space for both instructions and data.

Early computers were specifically designed for single tasks, requiring physical alterations to run different programs. They were inflexible and expensive to change.

A computer designed to execute a single task, requiring hardware modification to run different programs.

ENIAC (Electronic Numerical Integrator and Computer) helped with ballistic calculations during WWII. It was an early example of a programmable wired computer.

A computer architecture where instructions and data have separate memory spaces, offering potentially faster processing as they can be accessed concurrently.

A type of computer designed for general-purpose tasks, such as everyday computing, web browsing, and software development, requiring flexibility and adaptability.

A type of computer designed for specific tasks, often embedded in devices with limited resources and specialized requirements.

A processing unit specifically designed for manipulating digital signals, commonly used in audio processing, image compression, and telecommunications.

The core component of a computer responsible for executing instructions and carrying out computations.

A crucial step in the process of building a computer, involving the design and implementation of the architecture, particularly the CPU.

A key component within the CPU, responsible for carrying out arithmetic and logical operations on data.

This computer architecture emerged in the 1980s as a response to the complexity of CISC by focusing on simplifying instructions and improving execution speeds. It utilizes a smaller set of instructions, which are executed within a single clock cycle, leading to efficient performance.

This architecture, developed in the 1970s-80s, focuses on providing a large set of complex instructions that can complete tasks with a single instruction. It is used in x86 processors designed by Intel.

This architecture aims to improve parallel instruction execution by using a single instruction word to hold multiple separate operations that can be completed concurrently. It is used in Intel Itanium processors.

A significant advantage of RISC architecture is its simplified design, leading to faster instruction execution and lower energy consumption compared to more complex architectures.

A major disadvantage of CISC architecture is its increased complexity, leading to higher energy consumption and potentially slower instruction execution compared to RISC architectures.

A significant advantage of VLIW architecture is its ability to execute multiple instructions simultaneously, leading to higher performance compared to architectures that process instructions sequentially.

A major disadvantage of VLIW architecture is the increased complexity for software developers, as they need to meticulously plan instruction execution for effective parallelism.

The development of RISC architecture was driven by the observation that a large number of complex instructions in CISC architectures were rarely used, leading to unnecessary complexity.

The Instruction Pointer (IP) is a register that stores the address of the next instruction to be executed in the code segment (CS). The IP is key to the flow of program execution.

The 8086 instruction set allows for accessing memory using a combination of a segment and an offset. The physical memory address is calculated by multiplying the segment value by 16 and adding the offset value.

The 8086 architecture introduces various addressing modes to access data and memory during program execution.

Direct addressing mode directly specifies the memory location for data access.

Indirect addressing uses a register to hold the memory address of the data.

Indexed addressing uses a base register and an index register to calculate the data address. It often involves an offset.

With displacement, an offset value is added to a base register to access data. The offset can be a constant or a variable.

The segmented memory model of the 8086 allows the system to address more memory (1 MB), promote modularity, and increase flexibility by dividing the memory into segments. Each segment is a 64 KB block and can be accessed with a 16-bit segment address, a 16-bit offset, and a 20-bit physical address.

A binary operation that multiplies the 8-bit value in AL by an 8-bit value from another register (typically BL), storing the 16-bit result in AX.

Performs 16-bit multiplication between the 16-bit value in AX and a 16-bit value from another register (typically BX). The high part of the result goes to DX, the lower part to AX.

Divides the value in AX by an 8-bit value from another register (typically BL). The quotient (result of division) is stored in AL, while the remainder is in AH.

Divides the combined value of DX:AX (32 bits) by a 16-bit value from another register (typically BX). The quotient is stored in AX, and the remainder in DX.

An instruction to shift bits of a value to the right. The least significant bit (LSB) is moved to the Carry Flag (CF), and the most significant bit (MSB) is replaced with 0.

Shifts the value stored in a memory location to the right by a specified number of positions.

Shifts the value in a register to the right by a specified number of positions. This is useful for dividing a number by powers of 2.

Shifts the value stored in a memory location to the right by a number of positions specified by the CL register.

The OR instruction sets a bit to 1 if either (or both) of the corresponding bits in the operands are 1. It performs a bitwise OR operation on two operands.

The XOR instruction sets a bit to 1 if only one of the corresponding bits in the operands is 1. It performs a bitwise exclusive OR operation on two operands.

The CMP instruction compares two operands by subtracting them but doesn't store the result. Instead, it updates the status flags based on the comparison outcome.

The Zero Flag (ZF) is set to 1 if the comparison results in zero (equal operands), indicating that the operands are equal.

The Sign Flag (SF) is set to 1 if the result of the comparison is negative, indicating that the first operand was smaller than the second.

The Carry Flag (CF) is set to 1 if a 'borrow' was needed during the subtraction operation (when the first operand was smaller than the second), indicating an underflow.

The Overflow Flag (OF) is set to 1 if an overflow occurs during the comparison operation. It indicates an incorrect result due to exceeding the capacity of the register.

The CMP instruction allows efficient comparison and branching in programs, facilitating decision-making based on the comparison result.