Computer Architecture: Fetch/Execute Cycle Overview

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Questions and Answers

What occurs first in the Store Fetch/Execute Cycle?

PC is transferred to MAR (correct)

MDR is transferred to IR

Program Counter is incremented

Data is copied from accumulator to MDR

What is the purpose of incrementing the Program Counter in the execution cycle?

To load the next instruction into MDR

To change the instruction type being executed

To prepare for the next instruction fetch (correct)

To reset the accumulator value

In the ADD Fetch/Execute Cycle, what operation is performed after transferring the instruction to the IR?

Loading the accumulator with the instruction result

Copying data from MAR to MDR

Transferring the address from IR to MAR (correct)

Adding the contents of MAR to IR

What key difference is noted in Step #4 of the Store Fetch/Execute Cycle compared to the ADD Fetch/Execute Cycle?

Accumulator copies data into MDR for LOAD and STORE Signup and view all the answers

Which statement accurately describes the role of the Memory Data Register (MDR) during the execution cycles?

It holds data temporarily before it is executed Signup and view all the answers

What is one of the main advantages of parallel buses over serial buses?

Higher data transmission rates due to simultaneous bit transmission Signup and view all the answers

Which characteristic best describes serial buses?

Transmit one bit at a time Signup and view all the answers

Which of the following is a typical application for parallel buses?

CPU buses and connections on computer motherboards Signup and view all the answers

What is a primary characteristic of point-to-point bus systems?

Useful for one-to-one device communication Signup and view all the answers

What is the significance of data movement instructions in computing?

They enable the transfer of data between memory and registers Signup and view all the answers

What step occurs after the Program Counter (PC) is incremented in the LMC Fetch/Execute cycle?

The Memory Address Register (MAR) is updated with the PC value. Signup and view all the answers

Which signal is NOT part of the data transfer process in the bus system?

Process Control Signup and view all the answers

What occurs when a branch instruction condition is false in the LMC?

The PC is set to the next instruction. Signup and view all the answers

In the context of the bus, which best describes its purpose?

To transfer data between locations within the computer system. Signup and view all the answers

Which of the following actions is performed by the Instruction Register (IR) during the Fetch/Execute cycle?

Holding the instruction currently being executed. Signup and view all the answers

What characterizes a simplex bus?

It supports communication in one direction only. Signup and view all the answers

Which of the following is NOT a characteristic of buses?

Amount of electric current supplied to devices. Signup and view all the answers

What is a defining feature of a multipoint bus?

It connects a single source to multiple destinations. Signup and view all the answers

Which bus transmission method allows communication in one direction at a time?

Half duplex Signup and view all the answers

What is meant by throughput in the context of bus characteristics?

The amount of data transferred per second. Signup and view all the answers

What is the primary characteristic of DRAM?

It is volatile and must be refreshed constantly. Signup and view all the answers

Which type of memory is known for being a nonvolatile storage option?

ROM Signup and view all the answers

How many locations can be addressed with 8 bits in an instruction's address portion?

256 locations Signup and view all the answers

Which of the following is true about the fetch-execute cycle?

Data and instructions are fetched from the same memory locations. Signup and view all the answers

What is a primary advantage of using Flash Memory?

It uses hot carrier injection for data storage. Signup and view all the answers

Which of the following describes a characteristic of EEPROM?

It can be electrically erased and reprogrammed. Signup and view all the answers

During the fetch phase of the fetch-execute cycle, what is transferred to the MAR?

The address from the program counter Signup and view all the answers

What does SRAM primarily provide in comparison to DRAM?

It offers faster access speeds but is more expensive. Signup and view all the answers

Which operation is not typically associated with Boolean logic?

Increment Signup and view all the answers

What does LIFO stand for in relation to stack instructions?

Last In, First Out Signup and view all the answers

Which of the following best describes SIMD?

Single Instruction, Multiple Data Signup and view all the answers

In the context of program control, which action does a subroutine call perform?

Transfers control to another part of the program Signup and view all the answers

Which instruction type is primarily concerned with manipulating individual data values?

Bit manipulation instructions Signup and view all the answers

What does an instruction set of a processor define?

The functions performed by the processor Signup and view all the answers

Which of the following is true about shift and rotate instructions?

They change the position of data bits. Signup and view all the answers

When performing decrementing on an integer, what is the expected outcome?

The value decreases by one. Signup and view all the answers

What is a characteristic of an explicit address in an instruction format?

It is included in the instruction. Signup and view all the answers

Which of the following is NOT a primary component of an instruction?

Destination Directory Signup and view all the answers

Which of the following describes a characteristic of bus throughput?

Data transfer rate in bits per second Signup and view all the answers

What type of bus allows communication in both directions, but only one at a time?

Half duplex bus Signup and view all the answers

Which type of interconnection method connects a single source to a single destination?

Point-to-point bus Signup and view all the answers

In terms of bus characteristics, which of the following reflects addressing capacity?

The maximum number of addresses that can be used Signup and view all the answers

Which factor is NOT generally considered a characteristic of a bus?

Number of processors supported Signup and view all the answers

Which operation involves the accumulator during the ADD Fetch/Execute Cycle?

Contents of the MDR are added to the contents of the accumulator. Signup and view all the answers

What is the correct sequence of steps when an instruction is being fetched?

PC to MAR, MDR to IR, IR[address] to MAR, A to MDR. Signup and view all the answers

During which step of the Store Fetch/Execute Cycle does data move from the accumulator to the MDR?

Step 4. Signup and view all the answers

What is the main purpose of the Program Counter in the fetch/execute cycle?

To store the address of the instruction to execute next. Signup and view all the answers

In the context of the Store Fetch/Execute Cycle, what specifically differentiates the operation in Step 4 for LOAD and STORE instructions?

LOAD transfers data to the accumulator, STORE transfers from it. Signup and view all the answers

What is the maximum number of locations that can be addressed with 32 bits in an instruction's address portion?

4,294,967,296 locations Signup and view all the answers

Which type of RAM must be refreshed thousands of times each second?

DRAM Signup and view all the answers

Which of the following statements about SRAM is correct?

It provides higher speeds than DRAM. Signup and view all the answers

Which type of memory is faster but has a slower rewrite time compared to RAM?

Flash Memory Signup and view all the answers

During the fetch phase of the fetch-execute cycle, what is the final action taken after loading the instruction from memory?

Separate the address portion from the instruction. Signup and view all the answers

What does EEPROM stand for?

Electrically Erasable Programmable Read-Only Memory Signup and view all the answers

In the fetch-execute cycle, what is the role of the Memory Address Register (MAR)?

To store the address of the instruction being fetched. Signup and view all the answers

Which of the following statements accurately describes the limitations of parallel buses?

They can be affected by radio-generated electrical interference. Signup and view all the answers

What is a key advantage of serial buses compared to parallel buses?

Higher throughput due to reduced electrical interference. Signup and view all the answers

In the context of data movement instructions, which statement is true?

They provide the greatest flexibility for handling memory and registers. Signup and view all the answers

What defines a multipoint bus system?

All devices share a single communication line. Signup and view all the answers

What is a distinctive feature of instructions regarding word size?

Word size can vary as per system architecture, such as 16, 32, or 64 bits. Signup and view all the answers

Which component is responsible for performing calculations and comparisons in a CPU?

Arithmetic Logic Unit Signup and view all the answers

What role does the Control Unit play in the CPU's operation?

Carries out the fetch/execute cycle Signup and view all the answers

Which register holds the instruction fetched from memory during the execution cycle?

Instruction Register Signup and view all the answers

What is a primary function of the Memory Data Register (MDR)?

Manages the transfer of data between memory and CPU Signup and view all the answers

How does the Memory Address Register (MAR) contribute to memory operations?

Holds the unique address for memory locations Signup and view all the answers

Which type of registers holds intermediate results and is user-visible?

General Purpose Registers Signup and view all the answers

What aspect of registers allows them to manipulate data quickly during execution?

They are directly manipulated by the Control Unit. Signup and view all the answers

Which statement best describes the Function of Status Registers?

They track the CPU status with Boolean flags. Signup and view all the answers

How does the fetch-execute cycle begin?

By incrementing the Program Count Register. Signup and view all the answers

What determines the size of the registers within the CPU?

Registers are designed for specific functions and size in bits. Signup and view all the answers

What type of instruction word size has largely been eliminated due to pipelining?

Variable instruction size architectures Signup and view all the answers

Which of the following is an addressing mode used in modern architectures?

Direct addressing Signup and view all the answers

What does the first phase of the instruction cycle achieve?

Fetching and decoding the instruction Signup and view all the answers

Which of the following best describes the role of registers in the fetch-execute cycle?

They hold temporary data and instructions. Signup and view all the answers

What is a characteristic of the Little Man Computer model?

It performs work following simple instructions described by three-digit numbers. Signup and view all the answers

Which type of memory is characterized as volatile?

RAM Signup and view all the answers

What is the function of the last two digits in the instruction format of the Little Man Computer?

Indicate a memory address Signup and view all the answers

Which of the following addressing modes is associated with directly accessing data in a register?

Register deferred addressing Signup and view all the answers

Study Notes

System Software and Computing Concepts - CPU and Memory

The course covers CPU components, registers, memory units, fetch-execute cycles, buses, and instruction/word formats.
Learning outcomes include describing a computer system's structure, components, and functions.
Key terms include instruction cycle, linear memory addressing, Little Man Computer (LMC), mnemonics, op code, stored program concept, and von Neumann architecture.
Major CPU components include the ALU (arithmetic logic unit) for calculations and comparisons, and the CU (control unit) for the fetch/execute cycle, commanding the ALU and managing data movement between the CPU registers and other hardware.
Subcomponents: the memory management unit and I/O interface, sometimes combined as a bus interface unit.
A system block diagram shows the CPU, ALU, control unit, memory and I/O interface, program counter.
The Little Man Computer (LMC) provides a simplified model of a computer.
DRAM is the most common type of RAM, inexpensive, less power-consuming, and requires data refreshing.
SRAM is faster and more expensive than DRAM.
ROM stores software that typically does not change during operation.

Concept of Registers

Registers are small, permanent storage locations within the CPU, specialized for specific tasks.
The control unit directly manipulates registers.
Registers hold data, addresses, or instructions in bit or byte sizes (not megabytes like memory).

Use of Registers

Registers act as scratchpads for currently running programs; they hold frequently accessed data.
Registers store CPU status and program execution information.
They hold next instruction addresses and signals from external devices.
General-purpose registers hold intermediate results or data (ex: loop counters) like LMC's calculator, and are commonly used in current CPUs.

Special-Purpose Registers

The program counter (PC), also known as the instruction pointer, indicates the next instruction.
The instruction register (IR) stores the fetched instruction from memory.
The memory address register (MAR) holds the memory address required for data retrieval or storage.
The memory data register (MDR) is a two-way register transferring data to and from memory.
Status registers contain CPU status, using flags (bit-sized Boolean variables) to track conditions like arithmetic errors (carry/overflow), power failure.

Register Operations

Registers store data from other registers and memory locations.
Common operations include addition, subtraction, data shifting/rotation, and testing for conditions like zero or positive.

Operation of Memory

Each memory location has a unique address.
Memory address registers (MAR) hold addresses fetched from instructions.
The CPU determines if the address is for a retrieval or storage operation.
Data transfers occur between the memory data register (MDR) and memory.
The MDR is a two-way register.

Relationship between MAR, MDR, and Memory

The memory address register (MAR) decodes memory addresses.
The memory data register (MDR) stores the data that is being operated on or moved to or from memory.

MAR-MDR Example

Diagram shows the relationship between the memory address and data registers, and memory.

Visual Analogy of Memory

A visual representation of how the address decoder and memory data register work with each other to select a specific memory location.

Individual Memory Cell

Describes the mechanisms for writing and reading data to/from a memory location, using address lines, R/W line ("read/write"), and MDR line.

Memory Capacity

Memory capacity depends on the number of bits in the memory address register (MAR) and the size of the address portion of the instruction.
2ⁿ (where n = width of register in bits) determines the number of accessible memory locations.
Different register widths support different numbers of storage locations.

RAM: Random Access Memory

DRAM (Dynamic RAM) is the most common type, inexpensive, less power-consuming, and requires refreshing to maintain data.
SRAM (Static RAM) is faster and more expensive than DRAM. It is used in cache memory for high-speed access. Both are volatile.

Nonvolatile Memory

ROM (Read-Only Memory) stores software that typically does not change during operation and is nonvolatile.
EEPROM (Electrically Erasable Programmable ROM) is a form of ROM or programmable read-only memory that can be erased.
Flash memory is faster than hard disks, but has slower rewrite times than RAM.

Fetch-Execute Cycle

A two-step (Fetch & Execute) process.
Fetch: Instruction decoding and loading from memory to a register.
Execute: Performing the operation that the instruction requires.

LMC vs. CPU Fetch and Execute Cycle

Shows comparison between the operation of the LMC's fetch-execute cycle and a CPU's equivalent cycle.

Load Fetch/Execute Cycle

Detailed steps for loading data into the accumulator of the CPU.

Store Fetch/Execute Cycle

Shows how the CPU stores data from the accumulator to a memory location.

ADD Fetch/Execute Cycle

Detailed steps for the process of adding data to the accumulator of the CPU.

LMC Fetch/Execute (SUBTRACT)

Steps for the calculation of subtraction.

Bus

The physical connection enabling data transfer between locations in a computer system.
Composed of multiple lines (conductors) that carry various signals.
Four common signal types are data, addressing, control, and power (sometimes).

Bus Characteristics

Number of conductors and data width.
Addressing capacity.
Signal throughput rate.
Distance limitations.

Bus Categorizations

Parallel vs serial buses: comparison in data transfer speeds and complexity.
Direction of transmission (simple, half-duplex, full-duplex).
Interconnection methods (point-to-point, multipoint).

Parallel vs Serial Buses

Parallel buses transfer multiple bits simultaneously
Serial buses transfer one bit at a time

Point-to-point vs Multipoint

Point-to-Point Buses connect two devices directly.
Multipoint buses connect multiple devices to a common device.

Classification of Instructions

Data Movement (Load/Store): most flexible, involves memory and registers.
Arithmetic: performing addition/subtraction/multiplication/division, integers and floating-point operations.
Boolean Logic: includes AND, XOR, NOT operations.
Single Operand Operations: negating, decrementing, incrementing, setting to zero.

More Instruction Classifications

Bit manipulation, flags, shift, rotate, program control, stack manipulation, multiple data instructions, and I/O and machine control.

Register Shifts and Rotates

Types of logical and arithmetic shift/rotate operations.

Program Control Instructions

Examples of program control instructions including jumps, branches, subroutine calls, and returns.

Stack Instructions

LIFO (Last-In, First-Out) method for organized data.
Stack instructions involve PUSH and POP operations.

Block of Memory as a Stack

PUSH: increments the stack pointer and stores data on the stack
POP: loads data from the stack by decrementing the stack pointer.

Multiple Data Instructions

SIMD (Single Instruction, Multiple Data) performs the single operation concurrently on multiple data.

Instruction Format Examples

Instruction Format

Instructions

Instructions are directions given to a computer.
Instruction sets define actions the processor performs.
Key components are number and complexity of instructions, data types, format, use of registers, and addressing.

Instruction Word Size

Fixed vs variable instruction sizes.
Most current architectures use 32 or 64-bit words.
Addressing modes (mode used by LMC, Register Deferred, immediate, indirect, indexed).

Quick Review Questions

Questions on the instruction cycle, von Neumann architecture, volatile/nonvolatile memory, registers, fetch-execute cycle, Little Man Computer, and memory.

Summary

The Little Man Computer provides an analogy to a computer's internal operations (input/output, arithmetic logic unit, memory).

Q&A

Section for questions and answers.

The next topic for the course is CPU and Memory.

Studying That Suits You

Use AI to generate personalized quizzes and flashcards to suit your learning preferences.

Description

This quiz explores the essential concepts related to the Fetch/Execute Cycle in computer architecture. You will test your understanding of the roles of the Program Counter, Memory Data Register, and various types of bus systems. Gain insights on data movement instructions and their significance in computing.