Computer Architecture Basics Quiz
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Questions and Answers

Which addressing mode uses a register to store the memory address?

  • PC-relative
  • Indexed
  • Register Indirect (correct)
  • Direct

    • In direct addressing, the memory address is part of the instruction?

    True (A)

    What are the two main components of an instruction format?

    opcode and operands

    For jumps, the ______ addressing mode is commonly used.

    <p>PC-relative</p> Signup and view all the answers

    Which of the following is NOT typically a class of instructions in an Instruction Set Architecture (ISA)?

    <p>Hardware Diagnostics (C)</p> Signup and view all the answers

    A von-Neumann architecture uses different instruction formats.

    <p>False (B)</p> Signup and view all the answers

    Why is a register file used?

    <p>for fast access to memory</p> Signup and view all the answers

    Match the register type with its primary function:

    <p>General Registers = Storing integers and addresses Floating Point Registers = Storing floating-point numbers System Registers = Storing program counter and status information Multimedia Registers = Optimized instructions for decoding and encoding video</p> Signup and view all the answers

    What is the key difference between UMA and NUMA architectures?

    <p>UMA has uniform memory access latency, while NUMA has non-uniform memory access latency. (C)</p> Signup and view all the answers

    In a SIMD architecture, different instructions are executed asynchronously on multiple data sets.

    <p>False (B)</p> Signup and view all the answers

    What is the primary function of the Instruction Set Architecture (ISA)?

    <p>defines the capabilities of the processor for the programmer</p> Signup and view all the answers

    Processors are considered binary compatible if they support the same ______.

    <p>ISA</p> Signup and view all the answers

    What is the advantage of aligning memory operands at an s-byte boundary, where the format size is s bytes?

    <p>Optimized bus transfer and fit within cache lines. (B)</p> Signup and view all the answers

    In immediate addressing mode, the actual operand value is stored in a register.

    <p>False (B)</p> Signup and view all the answers

    Which of the following is NOT a main subcategory of computer architecture?

    <p>Operating System Architecture (C)</p> Signup and view all the answers

    Match the memory architecture with its communication method:

    <p>Distributed Memory (DM) = Messages Shared Memory (SM) = Read/Write operation to global addresses</p> Signup and view all the answers

    Instruction Set Architecture includes the implementation of an entire computer system by assembling interacting hardware components.

    <p>False (B)</p> Signup and view all the answers

    Which of the following is NOT a typical data type format specified in an ISA?

    <p>Quantum entanglement states (C)</p> Signup and view all the answers

    Name three areas where computer architecture is particularly important due to program efficiency needs.

    <p>Realtime systems, Servers, Games and graphics</p> Signup and view all the answers

    ____ involves the implementation of the ISA within a processor.

    <p>Microarchitecture</p> Signup and view all the answers

    Match the following subcategories of computer architecture with their descriptions:

    <p>Instruction Set Architecture (ISA) = Machine language including the instruction set, word size, memory address modes, processor registers, and address and data formats. Microarchitecture = Implementation of the ISA (within a processor). System Architecture = Implementation of an entire computer system by assembling interacting hardware components.</p> Signup and view all the answers

    Which of the following is included in Instruction Set Architecture (ISA)?

    <p>Memory address modes (D)</p> Signup and view all the answers

    Different microarchitectures can implement the same Instruction Set Architecture (ISA).

    <p>True (A)</p> Signup and view all the answers

    What is the art of selecting and interconnecting hardware components to create computers?

    <p>Computer architecture</p> Signup and view all the answers

    Flashcards

    Computer Architecture

    The art of selecting and interconnecting hardware components to meet performance and cost goals.

    Instruction Set Architecture (ISA)

    The machine language including instruction set, word size, and memory addressing modes.

    Microarchitecture

    The specific implementation of the ISA within a processor, allowing for different designs of a CPU.

    System Architecture

    Assembly of interacting hardware components to form a complete computer system.

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    Real-time Systems

    Computer systems that respond to inputs within a strict time limit for immediate processing.

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    Instruction Pipelining

    A technique that allows overlapping execution of instructions to improve CPU efficiency.

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    Caches

    Small, fast storage areas that temporarily hold frequently accessed data to speed up performance.

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    Distributed Memory Systems

    Computer architecture where each processor has its own private memory, communicating via a network.

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    SIMD

    Synchronized execution of the same instruction on multiple data.

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    MIMD

    Asynchronous execution of different instructions on multiple data.

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    Distributed Memory - DM

    Nodes have private physical address space; uses message communication.

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    Shared Memory - SM

    System where all processors share one address space; use read/write operations.

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    Uniform Memory Access - UMA

    Access to shared memory is uniform; all processors see the same latency.

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    Non-Uniform Memory Access - NUMA

    Distributed memory system; local accesses are faster than remote ones.

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    Addressing Modes

    Methods for accessing operands, including immediate and register addressing.

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    Direct Addressing

    Memory address is part of the instruction itself.

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    Register Indirect Addressing

    Memory address is held within a register.

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    Indexed Addressing

    Combines register indirect with a fixed offset.

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    PC-relative Addressing

    Addresses for jumps are relative to the Program Counter.

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    Instruction Classes

    Types include data transfer, arithmetic, control flow, and I/O.

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    Registers

    Fast-access memory within the processor with short addresses.

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    General Registers

    Registers used for integers, addresses, or bit data.

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    Execution Modes

    Operating systems manage hardware in multiuser and multiprogramming conditions.

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    Study Notes

    Advanced Computer Architecture

    • The course is about Advanced Computer Architecture, offered by Michael Gerndt at the Technical University of Munich (TUM).
    • The lecture schedule includes Tuesday (12:30-14:00), and Friday sessions (12:15-13:45), in Hörsaal HS2.
    • The course will involve 6 ECTS and 4 SWS (semester work).
    • Students are expected to prepare materials at home, understand key terms/concepts, use online resources and prepare for student presentations.
    • Students may use MarginNote 4 (Mac only) or REMnote (remnote.com).
    • Quizzes during lectures will be multiple-choice questions about the lecture material.
    • The exam will be 90 minutes long; online; and including multiple-choice questions and free text.
    • Expected topics include the content of current processors, evaluation of different designs and the interaction of architectures, compiler technology and applications. Additionally, it will cover different classes of parallel architectures, their implementation concepts, the practical art of selecting and interconnecting hardware components to create computers; formal modeling of computer systems; Instruction Set Architecture (ISA), Machine language, Microarchitecture, System architecture; different memory technologies, VLIW processors, data parallel architectures, shared memory systems, distributed memory, and many more.
    • Additional aspects include concepts for Computer History, study material (books and web resources), and a discussion of the concept of an Edge-Cloud continuum.
    • The course also covers topics on the Serverless IoT Framework, Senior Homecare costs in Germany, Intel's core architectures (Knights Landing and Sapphire Rapids) and their characteristics (including core architecture, technology, and applications).
    • The study notes cover further information on computer architecture aspects, including Computer Architecture and Parallel Systems (CAPS), lecture organization, course quizzes, and the goals of the lecture.
    • Also addressed are topics on process technology, Moore's Law, 10 nm technology, different processor classes (Signal processors, Graphics processors, Vector processors), and related topics.
    • The study material includes descriptions of parallelism in hardware, parallel metrics, the hardware/software interface, memory hierarchy, caching, and corresponding principles.
    • The course includes discussions on fault tolerance, reliability, availability, virtualization, specific processor classes, network processors, Intel Tofino 2, domain-specific language for the packet forwarding plane, all about parallelism (including pipeline), and related topics.
    • Furthermore, covered are topics on memory hierarchy; memory disambiguation; ordering; and types of cache misses (cold misses, capacity misses, conflict misses), cache update strategies, cache replacement strategies, performance gain, instruction cache, trace cache, and cache optimizations (including methods for increasing bandwidth, reducing hit time, reducing miss penalty and reducing miss rate).
    • Specific topics include the concepts of different memory architectures (SRAM, DRAM, and the architecture of a DRAM chip) and corresponding characteristics. Furthermore, the documentation provides information on DIMMs and Virtual Memory, including the Memory Management Unit (MMU) and translation, including page table organization, and the different characteristics and properties of non-volatile memory types (ROM's types such as PROM & EPROM & FLASH), including NOR vs NAND Flash and their corresponding cell designs and technologies (SLC and MLC).
    • Topics extend to including descriptions of and comparisons between different memory and processor technologies (including 3D XPoint, Intel Optane SSDs, and the use of those technologies in computing systems).
    • Noteworthy is discussions of fault tolerance concepts (ECC), Chipkill memory and the design decisions to support a proper functioning of a chip multiprocessor, covering, among other aspects, shared vs private LLC, centralized vs distributed implementations of shared caches, shared memory architecture and including descriptions of the important memory models such as sequential consistency, processor consistency, and weak consistency, and corresponding examples.
    • Also addressed are aspects of various processor types (such as NVIDIA GPUs and specific architectures, such as the Hopper, and its streaming multiprocessors (including a description of CUDA, a GPU programming language)) along with examples of their programming (e.g., DAXPY in PTX and CUDA and further examples).
    • Finally, covered are aspects of various network topologies, including fully connected networks, linear arrays and tori, as well as multidimensional meshes and tori, hypercubes, k-ary trees, and fat trees.
    • Further aspects covered include different Network Interface (NI) implementations, their characteristics, flow control, and corresponding types, methods, and examples, including zero-copy interface mechanisms.

    Topic subtitles

    • Content (Advanced Computer Architectures)
    • Lecture schedule
    • Resources
    • Evaluation of different architectures
    • Classes of Parallel Architectures
    • Parallel Metrics
    • Fault Tolerance, Reliability, and Availability
    • Virtualization
    • Processor Classes
    • Network Processors
    • Computer Architecture-related topics
    • Process Technology
    • Memory Technology
    • Memory Hierarchies
    • Cache Hierarchy
    • Cache Organization
    • Cache Update Strategies
    • Cache Replacement Strategies
    • Cache Performance Gain
    • Cache Optimization techniques
    • Cache Accesses (Pipelining vs Serial)
    • Instruction Pipelining; Instruction Cycle
    • Pipeline Hazards; Hazard Classes
    • Code Generation and Instruction Scheduling (static vs dynamic)
    • Loop Unrolling, Software Pipelining and Loop Fusion
    • More Processor Classes
    • Compiler Support
    • Work Sharing through Explicit Tasking
    • Synchronization
    • Locks
    • Bus Traffic
    • Atomic Operations
    • Memory Consistency
    • Software Pipelining vs Loop Unrolling
    • Summary Compiler Optimizations
    • Floating Point and Vector Extensions to Processors
    • Instruction Set Architecture (ISA) details, topics, and examples
    • Comparison among different Instruction Set Architectures (e.g., x86, ARM, and RISC-V) and a look into the particular characteristics of different architectures like Intel Knights Landing (KNL) processor series.
    • Memory Architectures for different processors
    • Network Topologies
    • Networks
    • Hardware Prefetching
    • Software Prefetching
    • Cache Optimization techniques (higher associations, etc)

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    Related Documents

    Advanced Computer Architecture Lecture Notes PDF

    Description

    Test your knowledge on computer architecture with this quiz. Topics include addressing modes, instruction formats, and different architectures such as UMA and NUMA. Perfect for students studying computer science concepts.

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