Computer Architecture: Arithmetic Logic Units

The Arithmetical and Logical Unit (ALU) performs arithmetic (addition, subtraction, multiplication, division, modulo) and logical (AND, OR, NOT, XOR) operations.

Adding, subtracting, multiplying, and dividing are examples of arithmetic operations. AND, OR, and NOT are examples of logical operations.

A full adder is a circuit that adds two single bits and a carry-in bit, producing a sum bit and a carry-out bit.

A ripple carry adder is a type of adder where the carry-out of each full adder is connected to the carry-in of the next full adder, creating a ripple effect.

The speed of a ripple carry adder is limited by the propagation delay of the carry signal through the chain of full adders.

A binary bit used to indicate whether an operation is an addition or subtraction.

A process of converting a binary number to its two's complement representation by inverting each bit and adding 1, used to perform subtraction using addition.

A set of n bits used within a circuit to represent a binary number.

The carry-out from the previous adder stage (Cn-1), along with the two input bits (xn-1 and yn-1), are fed into the current adder.

A combination of adders and control logic that allows for both addition and subtraction of binary numbers by selecting the operation using the Add/Sub bit.

When numbers with very different magnitudes are involved in calculations, rounding errors can occur due to limited precision in floating-point representation. For example, in the equation M + m - M = 0, if M is a very large number and m is a very small number, the result can be inaccurate due to rounding. Similarly, M - M + m = m might return an incorrect value due to rounding effects.

Floating-point numbers can have non-precise representations due to the limited precision of their format. For example, the decimal number 0.3 cannot be represented exactly in a floating-point system, resulting in an approximation.

A floating-point adder/subtractor unit is a component responsible for performing addition and subtraction operations on floating-point numbers. It typically involves steps like comparing exponents, aligning mantissas, and performing the actual addition/subtraction operation.

The process involves aligning the mantissas of the two numbers by adjusting their exponents through shifting or scaling operations. The goal is to make the exponents equal before performing the actual addition or subtraction on the mantissas.

In some cases, one operand might be significantly smaller than the other. If the difference in exponents exceeds the number of bits available for the mantissa, the result effectively becomes equal to the larger operand. The smaller operand is considered negligible compared to the larger one.

A method of performing multiplication by breaking down the operands into smaller parts and then multiplying them individually. The partial products are then shifted and added together to obtain the final result.

The process of arranging the partial products in a way that allows for efficient addition using a single accumulator.

A type of memory that looks up specific values based on an input address. Often used for storing pre-calculated multiplication results.

A method of multiplication that utilizes a look-up table to significantly reduce the number of steps required. In this approach, the partial products are stored in the LUT and retrieved as needed.

In the concept of multiplication using a LUT, the Wr* designates write operations to specific registers or memory locations involved in the process.

Representing numbers using separate components for sign, exponent, and mantissa to efficiently represent very large or very small numbers.

The part of a floating-point representation that indicates the sign (positive or negative) of the number.

The part of a floating-point representation that determines the magnitude or size of the number.

The part of a floating-point representation that stores the significant digits of the number, representing its fractional part.

Floating-point representation is a method for representing numerical values, but it is not a direct representation of real numbers from mathematics.

In unsigned 8-bit representation, when adding and the carry bit (C) is 1, it indicates an overflow. The result is set to FFh, which represents the highest possible value in an 8-bit unsigned system.

In unsigned 8-bit representation, when subtracting and the carry bit (C) is 1, it indicates an underflow. The result is set to 00h, which represents the lowest possible value in an 8-bit unsigned system.

A multiplexer (MUX) is used to select the correct result based on the carry bit (C) and the operation (addition or subtraction).

The saturation arithmetic technique ensures that the result of an operation is confined within the valid range of the representation, preventing values from exceeding the maximum or falling below the minimum.

Two's complement representation is commonly used to represent signed numbers, allowing for both positive and negative values within a defined range. To perform subtraction using addition, we convert the negative number to its two's complement form and add it to the positive number. This operation simplifies the implementation of arithmetic circuits.