Combinational Circuits: Adders

Combinational Circuits Overview

• Combinational circuits covered include adders, subtractors, multipliers, comparators, decoders, demultiplexers, encoders, multiplexers, parity generators, and checkers.

Adders

• Binary adders perform binary number addition.
• Logic circuits discussed involve half adders, full adders, ripple adders, parallel adders, and carry look-ahead adders.

Half Adder

• It's a basic building block for complex adder circuits such as full adders and multiple-bit adders.
• A half adder performs binary addition of two single-bit inputs, A and B.
• It provides two outputs: SUM and CARRY.
• Logical Expression for SUM: Sum = A XOR B
• Logical Expression for CARRY: Carry = A AND B

Full Adder

• It cannot complete a full addition with only 2 single-bit inputs.
• It requires three inputs: a, b, and carry from the previous bit.
• Logical Expression for SUM: = A’ B’ C-IN + A’ B C-IN’ + A B’ C-IN’ + A B C-IN = C-IN (A’ B’ + AB) + C-IN’ (A’ B + A B’) = C-IN ⊕ A ⊕ B = ∑(1,2,4,7)
• Logical Expression for COUT: = A’ B C-IN + A B’ C-IN + A B C-IN’ + A B C-IN = A B + BC-IN + AC-IN = ∑(3,5,6,7)
• Cout = AB + C-IN (A XOR B)

Binary Subtractors

• Half subtractors are digital logic circuits for binary subtraction of two single-bit binary numbers.
• They have two inputs, A and B, and two outputs, DIFFERENCE and BORROW.
• DIFFERENCE output shows the difference between input bits.
• BORROW output indicates if borrowing was necessary.
• Diff= A'B+AB' = A XOR B
• Borrow = A'B

Full Subtractor

• Includes inputs for minuend bit (A), subtrahend bit (B), and borrow-in bit from the previous stage (Bin).
• Includes outputs for difference bit (Diff) and borrow-out bit for the next stage (Bout).
• D = A’B’Bin + A’BBin’ + AB’Bin’ + ABBin = Bin(A’B’ + AB) + Bin’(AB’ + A’B) = Bin( A XNOR B) + Bin’(A XOR B) = Bin (A XOR B)’ + Bin’(A XOR B) = Bin XOR (A XOR B) = (A XOR B) XOR Bin
• Bout = A’B’Bin + A’BBin’ + A’BBin + ABBin = A’Bin(B + B’) + A’B(Bin + Bin’) + BBin(A + A’) = A’Bin + A’B + BBin

Carry Look-ahead Adder

• Faster for binary number addition, reducing computation time.
• Uses Carry Propagator (P) and Carry Generator (G) signals
• The carry propagator is propagated to the next level, and the carry generator creates the output carry, ignoring the input carry.
• Pi = Ai⊕ Bi
• Gi = Ai · Bi
• Sumi = Pi ⊕ Ci
• Ci+1 = Gi + ( Pi · Ci)

Carry Save Adder (CSA)

• A parallel ensemble of k full-adders without horizontal connection
• Adds three k-bit integers (A, B, C) to produce two integers (C0, S)
• C0 + S = A + B + C
• The ith bit of the sum (Si) and the (i + 1)st bit of the carry (Ci0+1)
• Si = Ai ⊕ Bi ⊕ Ci
• C0i+1 = AiBi + AiCi + BiCi

Decimal or BCD Adder

• Used to perform the addition of BCD numbers.
• A BCD digit can have any of ten possible four-bit representations.
• Cout=K+Z8.Z4+Z8.Z2
• The BCD is represented by the carry output as: BCD=Cout S8 S4 S2 S1

Digital Adder to Array Multiplier

• A digital combinational circuit used for multiplying two binary numbers by employing an array of full adders and half adders.
• Fast multiplication method since the time it takes is how long it takes for the signals to propagate.
• For j multiplier bits and k multiplier we need j*k AND gates and (j-1)k-bit adders to produce a product of j+k bits.

Decoders

• Decoders asserts one of their 2n outputs based on one of their n inputs depending on a particular decoder.
• Also called n to 2n line decoder.

Decoder

• Uses an AND gate as the basic decoding element, its output is HIGH only when its all inputs are HIGH.
• Large sizes of decoders can be done by cascading smaller decoders with enable lines to form a decoder tree.

Demultiplexers

• Decoders with an enable input that function as demultiplexers.
• Receive information on a single line.
• Transmitting the information into one of their 2n possible output lines.

Multiplexers (MUX)

• A digital switch that connects data from one of n sources to the output with select inputs.
• Steers one of 2n inputs to a single output line, through the selection lines.
• Also known as data selectors.

Parity Generators and Checkers

• Advanced mode of communication that detects errors while data transmitting.
• A Parity Generator generates the parity bit in the transmitter.
• A Parity Checker monitors the parity in the receiver.
• Parity Generator is a combinational circuit that accepts an (n-1)-bit stream data and generates the additional bit that transmits with the bit stream.
• Uses an Xor gate, that implements a circuit with sums of even number of 1s and 0s with a pivotal role.
• The total number of 1s must be even, even parity

Even and Odd Parity

• Even Parity boolean Function exp = = A (B+C) +A((B’C)
• Odd Parity truth table generates an odd number of bits to transmit.