48 Questions
What occurs when processor A writes the value '1' in the memory location X?
The new data is written only to its cache and an 'invalidation for X' is communicated in the bus.
What is the main difference between the write invalidate protocol and the write update protocol?
The write update protocol updates all cached copies of a data item, while the write invalidate protocol only updates the cache.
What happens when processor B reads X again after processor A has written the value '1' in the memory location X?
The data block will come from processor A's cache.
What is the purpose of the 'invalidation for X' signal in the write invalidate protocol?
To notify other processors that the cache needs to be updated.
Why do most recent multiprocessors implement the write invalidate protocol?
Because it consumes less bandwidth than the write update protocol.
What happens when processor A reads X and there is a cache miss?
The data block is cached from memory and the bus is notified.
What is the role of the bus in the write invalidate protocol?
To communicate cache misses and 'invalidation for X' signals.
Why does processor B read X again after processor A has written the value '1' in the memory location X?
Because processor B has been notified that the cache needs to be updated.
What is the main difference between the write update protocol and the write invalidate protocol?
The write update protocol acts on individual words, while the write invalidate protocol acts on cache blocks
What is the benefit of the write update protocol in terms of delay between writing and reading data?
It reduces the delay between writing a word on a processor and reading the value written on another processor
What is the mechanism used in the write invalidate protocol to invalidate a block?
Snooping mechanism
What is the key to implementation in the write invalidate protocol?
Getting access to the memory bus
What is a characteristic of the write invalidate protocol?
It tends to generate less traffic in the memory bus
What is the purpose of the snooping mechanism in the write invalidate protocol?
To check whether other processors have the block in their caches
Why is the memory bus considered a bottleneck in SMP?
Because it can become congested with traffic
What is the difference between write through and write back caches?
Write through caches always send written data to memory, while write back caches do not
What happens when a block is dirty and a read request is received?
The dirty block is sent in response to the read request and the memory read/fetch operation is aborted.
What is the 'invalid' state in the cache coherence protocol?
The block is not present in the cache.
What happens when a block is written to in the local cache?
The block becomes 'exclusive' and is not updated in the main memory.
What is the purpose of the finite-state machine controller in the cache coherence protocol?
To implement the snooping mechanism and ensure cache coherence.
What is the snooping mechanism used for in the cache coherence protocol?
To detect and resolve cache coherence conflicts.
How does the cache coherence protocol handle a write request from the processor?
It sends a write request to the bus and invalidates the cache block.
What is the 'shared' state in the cache coherence protocol?
The block is present in one or more local caches and is shared among multiple processors.
What is the purpose of the write invalidate protocol?
To invalidate the cache blocks and ensure cache coherence.
What is the primary characteristic of MIMD architecture?
Multiple instruction streams and multiple data streams
What is the primary purpose of a shared address space in multiprocessors?
To allow multiple processors to share memory and resources
What is the main difference between symmetric (shared-memory) multiprocessors and distributed shared memory multiprocessors?
The memory organization and architecture
What is the primary advantage of using a hypervisor system in multiprocessors?
Enhanced flexibility through multiple operating systems
What is the main challenge in designing a multiprocessor system?
Avoiding bottlenecks in the architecture
What is the primary benefit of using multiple processors in a system?
Improved performance through parallel processing
What is the main distinction between a multiprocessor and a multicore system?
The physical architecture of the system
What is the primary purpose of a shared memory in a multiprocessor system?
To provide a shared resource for multiple processors
What is the main characteristic of Symmetric Multiprocessors (SMP) systems?
They have a centralized shared memory with uniform access time.
What is the main advantage of using large caches in Symmetric Multiprocessors (SMP) systems?
To avoid the memory bottleneck
What is the main difference between Symmetric Multiprocessors (SMP) and Distributed Shared Memory (DSM) systems?
DSM has a non-uniform access time to memory.
What is the main advantage of using Distributed Shared Memory (DSM) systems?
To increase the memory bandwidth and reduce access latency
What is the main characteristic of Multiple Instruction, Multiple Data (MIMD) systems?
They use multiple instruction streams and multiple data streams.
What is the main purpose of using caches in multiprocessing systems?
To reduce the memory access latency
What is the main advantage of using multiprocessing systems?
To increase the processing power
What is the main characteristic of parallel processing systems?
They use multiple processors to execute multiple tasks
What is the primary function of a directory in a distributed cache coherence system?
To manage the state of every block that may be cached
What is the main advantage of distributing the directory along with the memory in a cache coherence system?
Scalability in multicore environments
What is the primary difference between a snooping protocol and a directory-based protocol?
Snooping uses message passing, while directory-based uses bus snooping
In a multicomputer system, why is there no cache coherence problem with respect to other computers?
Because each computer has its own independent memory and address space
What is the primary reason for using multithreading in parallel processing?
To exploit thread-level parallelism
What is the benefit of using a directory-based protocol in a distributed cache coherence system?
Scalability in multicore environments
What is the primary advantage of using a distributed directory in a cache coherence system?
Scalability in multicore environments
What is the characteristic of a directory-based protocol in a cache coherence system?
Uses message passing between nodes
Study Notes
Cache Coherence Protocols
- There are two main cache coherence protocols: write invalidate and write update.
- Write invalidate protocol acts on cache blocks, while write update protocol acts on individual words.
- In write invalidate protocol, only the first write of any word within a block needs to generate an invalidation, and it tends to generate less traffic in the memory bus.
Write Invalidate Protocol
- It requires a block invalidation when a word is written in a cache block.
- The block invalidation is done by sending the block address through the bus, and the other processors snoop on the bus to invalidate the block.
- It relies on serialized writes, which are forced by the need to get access to the bus as an exclusive resource.
- In write through cache, all written data are always sent to the memory, ensuring the most recent value of a data item can always be fetched from memory.
- In write back cache, if a block is clean (shared), the protocol acts like the write through approach.
Write Invalidate Protocol Example
- A processor reads a memory location, causing a cache miss, and the data block is cached.
- Another processor reads the same memory location, also causing a cache miss, and the data is cached.
- When a processor writes to the memory location, the new data goes only to its cache, and an invalidation is communicated through the bus.
- When the other processor reads the memory location again, it notices the invalidation, and the data block is fetched from the first processor's cache instead of memory.
Write Update Protocol
- It updates all cached copies of a data item when that item is written.
- It must broadcast all writes to shared cache lines, which consumes more bandwidth than the write invalidate protocol.
- Most recent multiprocessors have opted to implement a write invalidate protocol.
Cache Coherence Protocol States
- A cache block can be in one of three states: invalid, shared, or modified (exclusive).
- The state changes from invalid to shared when the block is first read, and to exclusive when the block is first written.
- The state transitions are triggered by requests from the CPU or the bus.
- A finite-state machine controller is implemented in each core to manage the state transitions.
Multiple Instruction, Multiple Data (MIMD) Systems
- MIMD architecture is related to multiprocessors, where different instructions can work on different data in parallel.
- Multiprocessors are computers consisting of tightly coupled processors controlled by a single operating system, sharing memory through a shared address space.
Memory Organization
- Multiple processors can share:
- Cache memory, main memory, and I/O system
- Main memory and I/O system
- I/O system
- Nothing, communicating through networks
- Feasibility of options depends on project requirements and avoiding bottlenecks in architecture.
Symmetric (Shared-Memory) Multiprocessors - SMP
- SMP are centralized shared-memory multiprocessors with 32 cores or less, sharing a single centralized memory.
- Each processor has equal access to memory, with a uniform access time (UMA) to all memory.
- SMP can use large caches and many buses to avoid memory and bus bottlenecks.
Distributed Shared Memory - DSM
- DSM has a larger processor number (e.g., 16 to 64 cores), using distributed memory to increase bandwidth and reduce access latency.
- Communication among processors is more complex than SMP, requiring more effort in software to take advantage of increased memory bandwidth.
- DSM has nonuniform memory access (NUMA), with access time depending on the location of a data word in memory.
Distributed Shared Memory (DSM) Architecture
- Each processing node can be a multicore with its own memory and I/O system in a multiprocessor chip.
- A directory keeps the state of every block that may be cached, including which caches have copies, whether it is dirty, and the block status.
- The directory is distributed along with the memory, with each directory responsible for tracking caches that share memory addresses.
Cache Coherence in DSM
- The directory-based protocol uses message passing between nodes, rather than snooping on the bus.
- The protocol needs to know which node has the block to make the invalidation, keeping information on which processors have each memory block.
Multicomputers
- Multicomputers are processors with independent memories and address spaces, with no cache coherence problem.
- However, cache coherence problems still exist within each computer.
Thread-Level Parallelism
- Multithreading is increasingly used to exploit explicit parallelism, with threads controlled by the programmer.
- This is in contrast to Instruction-Level Parallelism (ILP), which is already well-explored and limited.
Learn about cache coherence protocols, including write invalidate and write update protocols, and how they handle cache blocks and individual words.
Make Your Own Quizzes and Flashcards
Convert your notes into interactive study material.
Get started for free
