ARM Architecture Cache Quiz

Chapter 4: Cache Memory

• Computer memory is organized into a hierarchy, with processor registers at the top, followed by cache levels (L1, L2, etc.), main memory (DRAM), and external memory (hard drives, tapes).
• Cost per bit increases as you move down the hierarchy, but access time slows.
• Cache memory automatically stores copies of recently used data from main memory.
• Cache design elements involve cache addresses, cache size, mapping functions, replacement algorithms, write policies, and line size.
• Locality of reference: Memory access patterns tend to cluster, meaning that the recently accessed data is likely to be accessed again soon. This is exploited by caches to improve performance.
• Cache organization: Organized as direct-mapped, associative, or set-associative caches.
• Direct mapping: Each block of main memory maps to a unique cache line.
• Associative mapping: Each block of main memory can be loaded into any cache line.
• Set-associative mapping: A compromise; a block of memory can be mapped into any line within a particular set.
• Write policy: either "write-through" (updates written to both cache and main memory simultaneously) or "write-back" (updates only to cache, with a "dirty" bit marking those needing write-back).
• Cache size: The cache size is a trade-off between cost and performance. Ideally, balance the cost/bit of the smallest memory with the cache speed.

4.1 Computer Memory System Overview

• Characteristics of memory systems: Capacity, location (internal/external), unit of transfer (word/block), access method (sequential/direct/random/associative), and performance (access time/cycle time/transfer rate).
• Different physical memory types exist, including semiconductor, magnetic surface, optical, and magneto-optical.
• Memory can be volatile (data lost when power is off) or nonvolatile.
• Internal memory is often equated with main memory but also includes processor registers and cache.
• External memory includes devices connected through I/O modules (disks, tapes).

4.2 Cache Memory Principles

• Cache memory is designed to achieve the speed of the fastest semiconductor memories while offering a large memory capacity.
• It stores copies of frequently used portions of main memory.
• It is checked for the desired data first, before accessing main memory.

4.3 Elements of Cache Design

• Cache addresses: Logical and physical addresses are used, often with a memory management unit (MMU) to translate virtual addresses.
• Cache size: Capacity needs to balance cost per bit/access time tradeoff.
• Mapping functions: Techniques utilized for mapping main memory blocks to cache lines (direct, associative, set associative)
• Replacement algorithms: Determine which block in the cache to replace when the cache is full (Least Recently Used (LRU), First-In-First-Out (FIFO), Least Frequently Used (LFU), random).
• Write policies: Strategies for updating main memory when data in the cache is modified (write-through, write-back).
• Line size: The block size of data transferred between main memory and the cache.

4.4 Pentium 4 Cache Organization

• Pentium 4 organization: Used three levels of cache (L1 instruction, L1 data, L2 caches).
• Uses a four-way set-associative organization for L1 data cache.
• Includes an out-of-order execution logic enabling parallel operations.
• Use of split caches (instruction and data) for performance improvements.

4.5 ARM Cache Organization

• ARM cache organization: Evolved over time, using unified caches in early models and split (instruction/data) caches in later models.
• Most modern designs use a set-associative organization with varying associativity and line size depending on the specific ARM processor.
• Write-buffer for improved write performance.

4.6 Recommended Reading

• A list of article recommendations.

4.7 Key Terms, Review Questions and Problems

• Key terms are defined. Questions and problems relating to the material are listed
• Includes examples.