Advanced Computer Architecture CS-2 Lecture 1: Introduction and Basics

Dr. Muhammad Asif teaches Machine Learning, Deep Learning, and Natural Language Processing.

Attendance is mandatory in the Tuesday lecture from 1:30 PM to 4:30 PM.

Students are encouraged to work on homework to truly understand the material.

All students can collaborate on homework writeups.

The reference book mentioned is 'Computer Systems: A Programmer's Perspective, 3/E'.

Dr. Muhammad Asif teaches Numerical Optimization and Optical Networks.

The flag register has a bit called Overflow Flag (O) that indicates the overflow of a high-order bit after an arithmetic operation.

The Trap Flag (T) in the flag register enables the processor to execute in single-step mode.

If Direction Flag (D) is set to 1, the registers are automatically incremented during string instructions.

The Interrupt Flag (I) in the flag register enables external interrupts when set to 0.

The I/O Privilege Level field (IOPL) in the flag register defines the privilege level of the current process.

The VM flag bit in the flag register selects real mode operation in a protected mode system.

The VI flag in Pentium-Pentium 4 microprocessors is a copy of the virtual interrupt flag bit.

The VIP Flag is used to provide virtual interrupt flags and pending information to the Pentium-Pentium 4 microprocessors.

The ID Flag indicates that Pentium-Pentium 4 processors do not support the CPUID instruction.

The Memory Buffer Register (MBR) is also known as the Memory Data Register.

The Instruction Buffer Register (IBR) holds the opcode of the currently fetched instruction.

The Accumulator (AC) in CPU registers is used for arithmetic and logical operations.

4-address instructions need to specify 0~4 addresses in the instructions

2-address instructions are classified separately from 4-address instructions

The instruction size for 4-address instructions is 14 bytes

The memory accessible for 4-address instructions is 16 KB

If the data bus is of 1-byte, then a maximum of 1 byte of data can be fetched from memory to CPU in one clock cycle

Direct addressing mode requires a logical address to access data.

In direct addressing mode, the offset part is known as the effective address.

Offset in direct addressing mode is not specified directly as part of the instruction.

Assembler computes the offset value for memory labels declared using DB, DW, LABEL, etc.

Direct addressing mode is ideal for addressing complex data types like arrays.

In direct addressing mode, each array element can be accessed efficiently using a loop structure.