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Questions and Answers
What is the purpose of the ADCR in ADC – LPC 2148?
What is the purpose of the ADCR in ADC – LPC 2148?
- To perform mathematical operations
- To control the settings of the ADC (correct)
- To initialize the digital output pins
- To manage the global data register
What is the specified maximum ADC clock frequency in LPC 2148?
What is the specified maximum ADC clock frequency in LPC 2148?
- 4.5 MHz (correct)
- 8 MHz
- 10 MHz
- 2 MHz
In the ADC configuration, what should the Start Bits 24:26 be set to in order to initiate a conversion?
In the ADC configuration, what should the Start Bits 24:26 be set to in order to initiate a conversion?
- 111
- 010
- 001 (correct)
- 000
Which of the following registers is NOT specific to a particular channel in the LPC 2148 ADC?
Which of the following registers is NOT specific to a particular channel in the LPC 2148 ADC?
What binary value corresponds to the Clkdiv setting for the ADC in this configuration?
What binary value corresponds to the Clkdiv setting for the ADC in this configuration?
Flashcards
ADC control register
ADC control register
A register that controls the Analog-to-Digital Converter (ADC) settings.
ADC Data Register
ADC Data Register
Used to store the converted digital data.
ADCR (ADC control Register)
ADCR (ADC control Register)
A specific register that controls ADC operations.
CLKDIV (clock divider)
CLKDIV (clock divider)
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ADC clock max value
ADC clock max value
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Study Notes
ADC - LPC2148
-
ADC Control Register (ADCR):
- Bit 31-28: RESERVED
- Bit 27: EDGE
- Bit 26: START
- Bit 24-23: RESERVED
- Bit 22-21: PDN
- Bit 20-19: RESERVED
- Bit 18-17: CLKS
- Bit 16: BURST
- Bit 15-8: CLKDIV
- Bit 7-0: SEL
-
ADC Data Register (ADDR):
- Bit 15-6: RESULT
- Bit 23-16: RESERVED
- Bit 26-24: CHN
- Bit 29-27: RESERVED
- Bit 30: OVERRUN
- Bit 31: DONE
-
ADC Global Data Register (ADGDR/AD1GDR):
- Bits 5-0: RESERVED
- Bits 15-6: RESULT (binary fraction) for A/D conversion, based on AIN pin and VDDA.
- Bits 23-16: RESERVED
- Bits 26-24: CHN (channels during conversion)
- Bit 29-27: RESERVED
- Bit 30: OVERRUN
- Bit 31: DONE
-
CLKS field in ADCR:
- Value 000: 10 bits (0 to 1023)
- Value 001: 9 bits (0 to 511)
- Value 010: 8 bits (0 to 255)
- Value 011: 7bits (0 to 127)
- Value 100: 6 bits (0 to 63)
- Value 101: 5 bits (0 to 31)
- Value 110: 4 bits (0 to 15)
- Value 111: 3 bits (0 to 7)
-
Burst = 1 (Repeat Mode):
- The AD converter repeatedly converts at rate selected by CLKS field, scanning through pins. First conversion corresponds to least significant bit in SEL field. Repeated conversions can end by clearing the BURST bit.
-
Start Bits (24-26):
- Must be 001 to initiate conversion.
-
Maximum value of ADC clock: 4.5 MHz
-
CLKDIV similar to the PR value for other peripherals.
Other Considerations
- ADCR: Selecting pins (SEL), division of VPB clock (CLKDIV), burst mode (BURST).
- ADDR/ADGDR: Contains results of conversions, status flags (DONE, OVERRUN).
- Software control of conversions (CLKS, START bits).
- Channel selection (bits 26-24 in ADGDR).
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