Embedded Systems

Which of the following statements best describes an asynchronous digital system?

It is difficult to design and troubleshoot because the output can change states anytime one or more of the inputs change

As a general rule for stable flip-flop triggering, the clock pulse rise and fall times must be

very short

The asynchronous transfer of data between I-K storage registers can easily be accomplished using the:

PRESET and CLEAR inputs only.

The new IEEE/ANSI symbols for latches and flip-flop use the letter "C" to denotes

the SET and RESET inputs Signup and view all the answers

A "D" flip-flop with a PGT clock is in the CLEAR state. Which of the following input actions will cause it to change states?

CLK = PGT, D = 1 Signup and view all the answers

Asynchronous flip flop preset and clear inputs generally:

act as manual overrides that cause the outputs to change states regardless of the inputs or rock transitions. Signup and view all the answers

Forcing the SET input LOW on a NAND gate latch generates outputs of:

Q=1 and Q'=0 Signup and view all the answers

The MOD number of a counter:

indicates the number of possible counter output states Signup and view all the answers

Which of the following circuit parameters would be most likely to limit thes maximum operating frequency of an IC flip flop?

Propagation delay time Signup and view all the answers

Which of the following methods would be used to disable the PRESET (PRE) and CLEAR (CLR) inputs to a clocked flip-flop in a circuit application where they are NOT used

Connect the PRE and CLk inputs to a HIGH logic level. Signup and view all the answers

The setup time of a clocked flip-flop is

the minimum amount of time that an output must remain stable before an active clock transition Signup and view all the answers

A 15 MHZ clock signal is applied to an eight-flip-flop binary counter. Which of the following le indicates the proper MOD number, and maximum number of counts? maximum count, and output frequency of the circuit?

MOD 256, 256 counts, 255 maximum count, and 5,859.38 Hz Signup and view all the answers

Which statement best describes the operation of a NGT-triggered D flip-flop?

The logic level at the D input is transferred to Q on NGT of CLK Signup and view all the answers

Which of the following best describes the characteristics of a MOD-16 counter?

Sixteen possible counts, a maximum count of 1510, and frequency division by a factor of sixteen Signup and view all the answers

The clockec S-C flip-flop in Figure 5-1 is synchronized by the CLK puise when

the clock pulse transitions from LOW to HIGH Signup and view all the answers

Which of the following statements regarding the small triangles in the TEEE/ANSI symbols for flip flops is TRUE?

A triangle external to the rectangle means edge triggered and internal triangles indicate active LOW inputs Signup and view all the answers

The preset and clear inputs to a flip flop are HIGH (1). Which of the following is TRUE

The Q is in an ambiguous state. Signup and view all the answers

The combination of Q=1 and Q' = 0 defines the:

Flip flop set state. Signup and view all the answers

Select tie statement that best describes the two possible output states of a flip-flop

The output Q is HIGH and the Q 'output is LOW. Signup and view all the answers

A primary difference between a clocked J-K flip-flop and a clocked S-C flip-flop is the J-K's ability to:

toggle or change states when J= 1, K=1, and a clock transition occurs Signup and view all the answers

The difference between a D-latch and an edge-triggered D-type flip-flop is that the latch:

always latches" the Q output to the D input regardless of other inputs. Signup and view all the answers

Which of the following logic devices is specifically designed to produce clean. fast-changing output signals?

Schmitt-trigger Signup and view all the answers

What is the output state of a MOD 64 counter after 92 input pulses if the starting state is 000000?

011100 sub 2 Signup and view all the answers

Which of the following alternative logic gates would normally be used as a NAND latch equivalent representation?

active HIGH Input NOR gates Signup and view all the answers

What type of multivibrator produces a continuous pulse train?

Astable Signup and view all the answers

Three flip-flops are wired together as a binary counter and the input clock 15A HP) frequency is 600 Hz. What is the output frequency of the highest order Q cutput?

120 Hz Signup and view all the answers

An Internal designated as edge-triggered is primarily responsible for certain flip flops to be

Edge-detection circuit Signup and view all the answers

What factors determine the duration of the quasi-stable output pulse from a one-shot multivibrator?

An external resistor and capacitor Signup and view all the answers

Which of the following is the most common use of flip-flops?

Storage registers Signup and view all the answers

Select the statement that best describes the operation of retriggerable and non-retriggerable one-shot multivibrators.

A retriggerable one-shot must return to its stable state before it can be retriggered. Signup and view all the answers

An astable multivibrator:

All of the above Signup and view all the answers

Which of the following can result from a slow input signal transition?

Both B and C Signup and view all the answers

What type: of multivibrator has no stable state

both a and c Signup and view all the answers

How many shift pulses would be required to settally shift the contents of whe six stage register to another?

6 Signup and view all the answers

Which of the following logic devices has only one stabile state?

Monostable multivibrator Signup and view all the answers

Which statement best describes the action of a NAND gate latch?

The SET input is normally LOW, the CLEAR input is normally HIGH, the SET input is pulsed HIGH to change the outputs. Signup and view all the answers

A primary difference between a D flip-flop and the JK and S-C flip-flops is the fact that

a "D" flip-flop has only one control input and one clock input Signup and view all the answers

The ABEL statement Q = (D&EN) # IQBAR means that the output Q will be:

LOW if D and EN variables are HIGH, or if is LOW. Signup and view all the answers