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Questions and Answers
Which of the following statements best describes an asynchronous digital system?
Which of the following statements best describes an asynchronous digital system?
- It is difficult to design and troubleshoot because the output can change states anytime one or more of the inputs change (correct)
- It is easy to design and troubleshoot because the output state is independent of the inputs
- it is difficult to design and troubleshoot because the output cannot change states unless a clock input is syrchmnized to the SET and CLEAR inputs.
- is easy to design and troubleshoot because the exact times at which the output can change states is determined by a clock signal
As a general rule for stable flip-flop triggering, the clock pulse rise and fall times must be
As a general rule for stable flip-flop triggering, the clock pulse rise and fall times must be
- at a maximum value to enable the input control signals to stabilize.
- very short (correct)
- of to consequence as long as the levels are within the determinate range of values
- very long
The asynchronous transfer of data between I-K storage registers can easily be accomplished using the:
The asynchronous transfer of data between I-K storage registers can easily be accomplished using the:
- Clock and the input J-K control signal.
- J-K control signals only
- PRESET and CLEAR inputs only. (correct)
- Clock with the PRESET and CLEAR inputs.
The new IEEE/ANSI symbols for latches and flip-flop use the letter "C" to denotes
The new IEEE/ANSI symbols for latches and flip-flop use the letter "C" to denotes
A "D" flip-flop with a PGT clock is in the CLEAR state. Which of the following input actions will cause it to change states?
A "D" flip-flop with a PGT clock is in the CLEAR state. Which of the following input actions will cause it to change states?
Asynchronous flip flop preset and clear inputs generally:
Asynchronous flip flop preset and clear inputs generally:
Forcing the SET input LOW on a NAND gate latch generates outputs of:
Forcing the SET input LOW on a NAND gate latch generates outputs of:
The MOD number of a counter:
The MOD number of a counter:
Which of the following circuit parameters would be most likely to limit thes maximum operating frequency of an IC flip flop?
Which of the following circuit parameters would be most likely to limit thes maximum operating frequency of an IC flip flop?
Which of the following methods would be used to disable the PRESET (PRE) and CLEAR (CLR) inputs to a clocked flip-flop in a circuit application where they are NOT used
Which of the following methods would be used to disable the PRESET (PRE) and CLEAR (CLR) inputs to a clocked flip-flop in a circuit application where they are NOT used
The setup time of a clocked flip-flop is
The setup time of a clocked flip-flop is
A 15 MHZ clock signal is applied to an eight-flip-flop binary counter. Which of the following le indicates the proper MOD number, and maximum number of counts? maximum count, and output frequency of the circuit?
A 15 MHZ clock signal is applied to an eight-flip-flop binary counter. Which of the following le indicates the proper MOD number, and maximum number of counts? maximum count, and output frequency of the circuit?
Which statement best describes the operation of a NGT-triggered D flip-flop?
Which statement best describes the operation of a NGT-triggered D flip-flop?
Which of the following best describes the characteristics of a MOD-16 counter?
Which of the following best describes the characteristics of a MOD-16 counter?
The clockec S-C flip-flop in Figure 5-1 is synchronized by the CLK puise when
The clockec S-C flip-flop in Figure 5-1 is synchronized by the CLK puise when
Which of the following statements regarding the small triangles in the TEEE/ANSI symbols for flip flops is TRUE?
Which of the following statements regarding the small triangles in the TEEE/ANSI symbols for flip flops is TRUE?
The preset and clear inputs to a flip flop are HIGH (1). Which of the following is TRUE
The preset and clear inputs to a flip flop are HIGH (1). Which of the following is TRUE
The combination of Q=1 and Q' = 0 defines the:
The combination of Q=1 and Q' = 0 defines the:
Select tie statement that best describes the two possible output states of a flip-flop
Select tie statement that best describes the two possible output states of a flip-flop
A primary difference between a clocked J-K flip-flop and a clocked S-C flip-flop is the J-K's ability to:
A primary difference between a clocked J-K flip-flop and a clocked S-C flip-flop is the J-K's ability to:
The difference between a D-latch and an edge-triggered D-type flip-flop is that the latch:
The difference between a D-latch and an edge-triggered D-type flip-flop is that the latch:
Which of the following logic devices is specifically designed to produce clean. fast-changing output signals?
Which of the following logic devices is specifically designed to produce clean. fast-changing output signals?
What is the output state of a MOD 64 counter after 92 input pulses if the starting state is 000000?
What is the output state of a MOD 64 counter after 92 input pulses if the starting state is 000000?
Which of the following alternative logic gates would normally be used as a NAND latch equivalent representation?
Which of the following alternative logic gates would normally be used as a NAND latch equivalent representation?
What type of multivibrator produces a continuous pulse train?
What type of multivibrator produces a continuous pulse train?
Three flip-flops are wired together as a binary counter and the input clock 15A HP) frequency is 600 Hz. What is the output frequency of the highest order Q cutput?
Three flip-flops are wired together as a binary counter and the input clock 15A HP) frequency is 600 Hz. What is the output frequency of the highest order Q cutput?
An Internal designated as edge-triggered is primarily responsible for certain flip flops to be
An Internal designated as edge-triggered is primarily responsible for certain flip flops to be
What factors determine the duration of the quasi-stable output pulse from a one-shot multivibrator?
What factors determine the duration of the quasi-stable output pulse from a one-shot multivibrator?
Which of the following is the most common use of flip-flops?
Which of the following is the most common use of flip-flops?
Select the statement that best describes the operation of retriggerable and non-retriggerable one-shot multivibrators.
Select the statement that best describes the operation of retriggerable and non-retriggerable one-shot multivibrators.
An astable multivibrator:
An astable multivibrator:
Which of the following can result from a slow input signal transition?
Which of the following can result from a slow input signal transition?
What type: of multivibrator has no stable state
What type: of multivibrator has no stable state
How many shift pulses would be required to settally shift the contents of whe six stage register to another?
How many shift pulses would be required to settally shift the contents of whe six stage register to another?
Which of the following logic devices has only one stabile state?
Which of the following logic devices has only one stabile state?
Which statement best describes the action of a NAND gate latch?
Which statement best describes the action of a NAND gate latch?
A primary difference between a D flip-flop and the JK and S-C flip-flops is the fact that
A primary difference between a D flip-flop and the JK and S-C flip-flops is the fact that
The ABEL statement Q = (D&EN) # IQBAR means that the output Q will be:
The ABEL statement Q = (D&EN) # IQBAR means that the output Q will be:
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