Embedded Systems
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Questions and Answers

Which of the following statements best describes an asynchronous digital system?

  • It is difficult to design and troubleshoot because the output can change states anytime one or more of the inputs change (correct)
  • It is easy to design and troubleshoot because the output state is independent of the inputs
  • it is difficult to design and troubleshoot because the output cannot change states unless a clock input is syrchmnized to the SET and CLEAR inputs.
  • is easy to design and troubleshoot because the exact times at which the output can change states is determined by a clock signal

    • As a general rule for stable flip-flop triggering, the clock pulse rise and fall times must be

  • at a maximum value to enable the input control signals to stabilize.
  • very short (correct)
  • of to consequence as long as the levels are within the determinate range of values
  • very long

    • The asynchronous transfer of data between I-K storage registers can easily be accomplished using the:

  • Clock and the input J-K control signal.
  • J-K control signals only
  • PRESET and CLEAR inputs only. (correct)
  • Clock with the PRESET and CLEAR inputs.

    • The new IEEE/ANSI symbols for latches and flip-flop use the letter "C" to denotes

    <p>the SET and RESET inputs</p> Signup and view all the answers

    A "D" flip-flop with a PGT clock is in the CLEAR state. Which of the following input actions will cause it to change states?

    <p>CLK = PGT, D = 1</p> Signup and view all the answers

    Asynchronous flip flop preset and clear inputs generally:

    <p>act as manual overrides that cause the outputs to change states regardless of the inputs or rock transitions.</p> Signup and view all the answers

    Forcing the SET input LOW on a NAND gate latch generates outputs of:

    <p>Q=1 and Q'=0</p> Signup and view all the answers

    The MOD number of a counter:

    <p>indicates the number of possible counter output states</p> Signup and view all the answers

    Which of the following circuit parameters would be most likely to limit thes maximum operating frequency of an IC flip flop?

    <p>Propagation delay time</p> Signup and view all the answers

    Which of the following methods would be used to disable the PRESET (PRE) and CLEAR (CLR) inputs to a clocked flip-flop in a circuit application where they are NOT used

    <p>Connect the PRE and CLk inputs to a HIGH logic level.</p> Signup and view all the answers

    The setup time of a clocked flip-flop is

    <p>the minimum amount of time that an output must remain stable before an active clock transition</p> Signup and view all the answers

    A 15 MHZ clock signal is applied to an eight-flip-flop binary counter. Which of the following le indicates the proper MOD number, and maximum number of counts? maximum count, and output frequency of the circuit?

    <p>MOD 256, 256 counts, 255 maximum count, and 5,859.38 Hz</p> Signup and view all the answers

    Which statement best describes the operation of a NGT-triggered D flip-flop?

    <p>The logic level at the D input is transferred to Q on NGT of CLK</p> Signup and view all the answers

    Which of the following best describes the characteristics of a MOD-16 counter?

    <p>Sixteen possible counts, a maximum count of 1510, and frequency division by a factor of sixteen</p> Signup and view all the answers

    The clockec S-C flip-flop in Figure 5-1 is synchronized by the CLK puise when

    <p>the clock pulse transitions from LOW to HIGH</p> Signup and view all the answers

    Which of the following statements regarding the small triangles in the TEEE/ANSI symbols for flip flops is TRUE?

    <p>A triangle external to the rectangle means edge triggered and internal triangles indicate active LOW inputs</p> Signup and view all the answers

    The preset and clear inputs to a flip flop are HIGH (1). Which of the following is TRUE

    <p>The Q is in an ambiguous state.</p> Signup and view all the answers

    The combination of Q=1 and Q' = 0 defines the:

    <p>Flip flop set state.</p> Signup and view all the answers

    Select tie statement that best describes the two possible output states of a flip-flop

    <p>The output Q is HIGH and the Q 'output is LOW.</p> Signup and view all the answers

    A primary difference between a clocked J-K flip-flop and a clocked S-C flip-flop is the J-K's ability to:

    <p>toggle or change states when J= 1, K=1, and a clock transition occurs</p> Signup and view all the answers

    The difference between a D-latch and an edge-triggered D-type flip-flop is that the latch:

    <p>always latches&quot; the Q output to the D input regardless of other inputs.</p> Signup and view all the answers

    Which of the following logic devices is specifically designed to produce clean. fast-changing output signals?

    <p>Schmitt-trigger</p> Signup and view all the answers

    What is the output state of a MOD 64 counter after 92 input pulses if the starting state is 000000?

    <p>011100 sub 2</p> Signup and view all the answers

    Which of the following alternative logic gates would normally be used as a NAND latch equivalent representation?

    <p>active HIGH Input NOR gates</p> Signup and view all the answers

    What type of multivibrator produces a continuous pulse train?

    <p>Astable</p> Signup and view all the answers

    Three flip-flops are wired together as a binary counter and the input clock 15A HP) frequency is 600 Hz. What is the output frequency of the highest order Q cutput?

    <p>120 Hz</p> Signup and view all the answers

    An Internal designated as edge-triggered is primarily responsible for certain flip flops to be

    <p>Edge-detection circuit</p> Signup and view all the answers

    What factors determine the duration of the quasi-stable output pulse from a one-shot multivibrator?

    <p>An external resistor and capacitor</p> Signup and view all the answers

    Which of the following is the most common use of flip-flops?

    <p>Storage registers</p> Signup and view all the answers

    Select the statement that best describes the operation of retriggerable and non-retriggerable one-shot multivibrators.

    <p>A retriggerable one-shot must return to its stable state before it can be retriggered.</p> Signup and view all the answers

    An astable multivibrator:

    <p>All of the above</p> Signup and view all the answers

    Which of the following can result from a slow input signal transition?

    <p>Both B and C</p> Signup and view all the answers

    What type: of multivibrator has no stable state

    <p>both a and c</p> Signup and view all the answers

    How many shift pulses would be required to settally shift the contents of whe six stage register to another?

    <p>6</p> Signup and view all the answers

    Which of the following logic devices has only one stabile state?

    <p>Monostable multivibrator</p> Signup and view all the answers

    Which statement best describes the action of a NAND gate latch?

    <p>The SET input is normally LOW, the CLEAR input is normally HIGH, the SET input is pulsed HIGH to change the outputs.</p> Signup and view all the answers

    A primary difference between a D flip-flop and the JK and S-C flip-flops is the fact that

    <p>a &quot;D&quot; flip-flop has only one control input and one clock input</p> Signup and view all the answers

    The ABEL statement Q = (D&EN) # IQBAR means that the output Q will be:

    <p>LOW if D and EN variables are HIGH, or if is LOW.</p> Signup and view all the answers

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