8086 MPU I/O Interfacing

Study Notes

I/O data transfer in the 8088/8086 MPU can be byte-wide or word-wide.
I/O port numbers are 16-bits in length.
Output over AD0 … AD15, A16, A19 will hold Zero.
Data is transferred using AD0 … AD7; if a byte is transferred, one clock cycle is needed; if a word is transferred, two clock cycles are needed.
The processor sets IO/M to 0 to indicate that it is accessing I/O not memory.

Two types of I/O instructions: Direct I/O and Variable I/O.
Direct I/O: The port number is provided in the instruction; port numbers are 8-bits only (00H to FFH); only 256 ports are available.
Variable I/O: Uses 16-bit port number that resides in DX; DX is not an offset, but the actual port number; 64KByte I/O address space is available; up to 65536 byte-sized ports.

Each bus cycle is 4 clock cycles (4 T-States).
If the CPU is operating at 8 MHz, then each clock cycle is 125 ns long; length of a normal bus cycle is 4 x 125 ns = 500 ns.
External device connected to the microprocessor can expect the following timing requirements for a READ cycle:
- CPU produces the address on the address bus and maintains it for 1 clock cycle.
- External device has 1 clock cycle to decode and locate the location.
- External device produces the data and maintains it on the data bus for 2 clock cycles.

Idle state: No bus cycles required; the bus remains idle.
Wait state: States inserted between T3 and T4 of the current bus cycle; used to wait for very slow devices.

Place I/O devices within the memory address space of the processor.
Some of the memory space is dedicated to I/Os.
Reading from and writing to memory-mapped I/O devices uses the same exact instructions as reading from and writing to memory locations.