Topic 4(1) - Computer Function and Interconnection PDF

C S F 3 2 4 3 + Topic 4 – Part...

C S F 3 2 4 3 + Topic 4 – Part 1 Computer Function and Interconnection Computer Consist Of 3 Main Parts/ Components Computer system: (1) The external behavior of each component, that is, the data + and control signals that it exchanges with other components (2) The controls required to manage the use of the interconnection structure. + Learning Outcomes: 1. Understand Basic Structures: Identify and understand the fundamental structures used for interconnecting computer components. 2. Functional Overview: Gain a functional overview of how computer components interact and connect with each other. 3. Use of Buses: Examine and understand the role of buses in the interconnection of system components. 4. Interconnection Techniques: Compare different interconnection techniques and understand their applications in contemporary systems. + Computer Components ◼ Contemporary computer designs are based on concepts developed by John von Neumann at the Institute for Advanced Studies (IAS), Princeton ◼ Referred to as the von Neumann architecture and is based on three key concepts: ◼ Data and instructions are stored in a single read-write memory ◼ The contents of this memory are addressable by location, without regard to the type of data contained there ◼ Execution occurs in a sequential fashion (unless explicitly modified) from one instruction to the next ◼ Hardwired program ◼ The result of the process of connecting the various components in the desired configuration. The resulting “program” is in the form of hardware. + Hardware and Software Approaches Software A sequence of codes or instructions Software Part of the hardware interprets each instruction and generates control signals Provide a new sequence of codes for each new program instead of rewiring the hardware Major components: CPU I/O Instruction interpreter Components Module of general-purpose arithmetic and logic functions I/O Components + Input module Contains basic components for accepting data and instructions and converting them into an internal form of signals usable by the system Output module Means of reporting results  Memory Memory buffer MEMORY address register (MBR) register (MAR) Contains the data Specifies the to be written into address in memory memory or for the next read or receives the data write read from memory MAR I/O address I/O buffer register (I/OAR) register (I/OBR) Specifies a Used for the + particular I/O exchange of data device between an I/O module and the CPU MBR  Computer Components: Top Level View + Basic Instruction Cycle Instruction processing consists of two steps: 1) The processor reads (fetches) instructions from memory one at a time 2) Executes each instruction. + Fetch Cycle ◼ At the beginning of each instruction cycle the processor fetches an instruction from memory ◼ A register called the program counter (PC) holds the address of the instruction to be fetched next ◼ The processor increments the PC after each instruction fetch so that it will fetch the next instruction in sequence ◼ The fetched instruction is loaded into the instruction register (IR) ◼ The processor interprets the instruction and performs the required action Action Categories Data transferred from Data transferred to or processor to memory from a peripheral or from memory to device by transferring processor between the processor and an I/O module Processor- Processor- memory I/O Data Control processing An instruction may The processor may specify that the perform some sequence of execution arithmetic or logic be altered operation on data  The processor contains a single data register, called an accumulator (AC). Both + instructions and data are 16 bits long. Thus, it is convenient to organize memory using 16-bit words. The instruction format provides 4 bits for the opcode (type operation), so that there can be as many as 24 = 16 different opcodes, and up to 212 = 4096 (4K) words of memory can be directly addressed.  Example of + Program Execution  Instruction Cycle State Diagram + + Interrupts An interrupt is just that: an interruption of the normal sequence of execution. Interrupt is a signal sent to the processor to indicate an event that needs immediate attention, temporarily halting the current execution and allowing the system to respond to important or time-sensitive tasks. Interrupts help in efficient multitasking by allowing the CPU to handle external or internal events promptly. + Program Flow Control + Transfer of Control via Interrupts + Instruction Cycle With Interrupts + Program Timing: Short I/O Wait 1) User program code segments are shaded green 2) I/O program code segments are shaded gray + Program Timing: Long I/O Wait 1) User program code segments are shaded green 2) I/O program code segments are shaded gray Instruction Cycle State Diagram With Interrupts  Handling Interrupts Multiple Interrupts +  Transfer of Control Multiple Interrupts + + Time Sequence of Example Multiple Interrupts + I/O Function ◼ I/O module can exchange data directly with the processor ◼ Processor can read data from or write data to an I/O module ◼ Processor identifies a specific device that is controlled by a particular I/O module ◼ I/O instructions rather than memory referencing instructions ◼ In some cases it is desirable to allow I/O exchanges to occur directly with memory ◼ The processor grants to an I/O module the authority to read from or write to memory so that the I/O memory transfer can occur without tying up the processor ◼ The I/O module issues read or write commands to memory relieving the processor of responsibility for the exchange ◼ This operation is known as direct memory access (DMA) + Computer Modules (Components) The collection of paths connecting the various modules is called the interconnection structure. The design of this structure will depend on the exchanges that must be made among modules. + The interconnection structure must support the following types of transfers: Memory Processor I/O to or I/O to Processor to to from processor to I/O processor memory memory An I/O module is allowed to exchange data Processor Processor directly reads an Processor reads data Processor with instruction writes a from an I/O sends data memory or a unit of unit of data device via to the I/O without data from to memory an I/O device going memory module through the processor using direct memory access A communication pathway Signals transmitted by any connecting two or more one device are available for devices reception by all other devices attached to the bus Bus Interconnection Key characteristic is that it is a shared transmission medium If two devices transmit during the same time period their signals will overlap and become garbled Typically, a bus consists of multiple communication Computer systems contain a lines number of different buses that provide pathways Each line is capable of between components at transmitting signals representing binary 1 and binary 0 various levels of the computer system hierarchy System bus A bus that connects major The most common computer computer components (processor, memory, I/O) interconnection structures are based on the use of one or more system buses + Computer Bus Architecture Source: https://www.learncomputerscienceonline.com/computer-bus/ + Computer Bus Architecture Source: https://www.learncomputerscienceonline.com/computer-bus/ + Computer Bus Architecture Source: https://www.learncomputerscienceonline.com/computer-bus/ Source: https://www.learncomputerscienceonline.com/computer-bus/ Bus Interconnection Scheme Data Bus ◼ Data lines that provide a path for moving data among system modules ◼ May consist of 32, 64, 128, or more separate lines ◼ The number of lines is referred to as the width of the data bus ◼ The number of lines determines how many bits can be transferred at a time ◼ The width of the data bus is a key factor in determining overall system performance + Address Bus Control Bus ◼ Used to designate the source or ◼ Used to control the access and the destination of the data on the use of the data and address lines data bus ◼ If the processor wishes to ◼ Because the data and address lines read a word of data from are shared by all components there memory it puts the address of must be a means of controlling their the desired word on the use address lines ◼ Control signals transmit both ◼ Width determines the maximum command and timing information possible memory capacity of the among system modules system ◼ Timing signals indicate the validity ◼ Also used to address I/O ports of data and address information ◼ The higher order bits are used to select a particular ◼ Command signals specify operations module on the bus and the to be performed lower order bits select a memory location or I/O port within the module Control Bus  Bus Configurations + Elements of Bus Design Method of Type Timing Bus Width Arbitration/Binding Dedicated Centralized Synchronous Address Multiplexed Distributed Asynchronous Data Data Transfer Type Read Write Read-Modify-Write Read-after-write Block + Elements of Bus Design – Types ◼ Dedicated – assigned to a single function (e.g. address bus) or a physical subset of components (e.g. I/O bus connects all I/O modules). ◼ Multiplexed – a bus can be used for both addresses and data. In this case, an address valid control line is needed to determine whether the data is an address or data. Time multiplexing is using the same lines for multiple purposes. + Elements of Bus Design – Arbitration/ Binding ◼ Centralized – a single hardware device known as the bus controller (or arbiter) is responsible for allocating time on the bus. ◼ Distributed – there is no central controller. Each module has access control logic, and the modules act together to share the bus. In either case, the processor or I/O module is designated as a master for the purposes of transferring data and some other device is designated as a slave for the operation. + Timing of Synchronous Bus Operations ◼ Synchronous – the clock determines the occurrence of events on the bus. Timing of Asynchronous Bus Operations ◼ Asynchronous – timing does not involve a clock, instead one event on a bus follows and depends on some previous event. + Elements of Bus Design – Bus Width ◼ The width of a data bus refers to the number of bits (electrical wires) that it can carry at a time. ◼ The wider the bus width, the faster the data flow on the data bus, thus better system performance. ◼ E.g. 16-bit wide data bus can carry 16 bits of data simultaneously between the CPU and system components such as RAM.  Elements of Bus Design – Transfer Type + + Elements of Bus Design – Transfer Type + Point-to-Point Interconnect vs Shared Bus Principal reason for change At higher and higher data was the electrical rates it becomes constraints encountered increasingly difficult to with increasing the perform the synchronization frequency of wide and arbitration functions in a synchronous buses timely fashion A conventional shared bus on the same chip magnified Has lower latency, higher the difficulties of increasing data rate, and better bus data rate and reducing scalability bus latency to keep up with the processors +Quick Path Interconnect QPI ◼ Introduced in 2008 point-to-point ◼ Characteristics of QPI: interconnect ◼ Multiple direct connections approach ◼ Direct pairwise connections to other components eliminating the need for arbitration found in shared transmission systems ◼ Layered protocol architecture ◼ These processor level interconnects use a layered protocol architecture rather than the simple use of control signals found in shared bus arrangements ◼ Packetized data transfer ◼ Data are sent as a sequence of packets each of which includes control headers and error control codes  Multicore Configuration Using QPI + Peripheral Component Interconnect (PCI) ◼ A popular high bandwidth, processor independent bus that can function as a peripheral bus ◼ Delivers better system performance for high speed I/O subsystems ◼ PCI Special Interest Group (SIG) ◼ Created to develop further and maintain the compatibility of the PCI specifications ◼ PCI Express (PCIe) ◼ Point-to-point interconnect scheme intended to replace bus-based schemes such as PCI ◼ Key requirement is high capacity to support the needs of higher data rate I/O devices, such as Gigabit Ethernet ◼ Another requirement deals with the need to support time dependent data streams + PCIe Configuration  Comparison between PCI, PCI-e and QPI PCIe: Modern, high-speed, serial-based interface commonly used for high-performance components like GPUs. QPI: Specialized, high-bandwidth, serial connection mainly for inter-CPU and CPU-to-memory controller communication in servers. PCI: Older, parallel-based interface mainly used for legacy peripherals. Computer System Bus Functions Source: https://www.learncomputerscienceonline.com/computer-bus/ + Summary Computer Function and Interconnection Topic 4(1) ◼ Point-to-point interconnect ◼ Computer components ◼ QPI ◼ Computer function ◼ Instruction fetch and ◼ PCI execute ◼ Interrupts ◼ PCI express (PCIe) ◼ I/O function ◼ Interconnection structures ◼ Bus interconnection ◼ Bus structure ◼ Multiple bus hierarchies ◼ Elements of bus design