Reduced Combined Slides 2E6B (3) PDF

2 | The diode 2E6-B Objectives: To introduce the concept of non-linear circuit elements. To introduce the diode, and to analyse some circuits containing diodes. To use diodes as limiting, protecting, and half wave rectifying circuits. The diode is the most fundamental non-linear circuit element...

2 | The diode 2E6-B Objectives: To introduce the concept of non-linear circuit elements. To introduce the diode, and to analyse some circuits containing diodes. To use diodes as limiting, protecting, and half wave rectifying circuits. The diode is the most fundamental non-linear circuit element. It is a two-terminal device with the following circuit symbol: [reproduced from Sedra/Smith, 8th edition] Cathode (minus) at ground (tip of triangle) Anode (positive) at voltage supply [reproduced from Sedra/Smith, 8th edition] Physical mark on diodes indicates cathode through thick black ring on cylindrical diodes, shorter leg or kink in anode The ideal diode’s terminal characteristics can be interpreted as: If a negative voltage is applied (relative to the reference direction): no current flows and the diode behaves as an open circuit. If a positive voltage is applied (relative to the reference direction): current flows and the diode behaves as a short circuit. [figures reproduced from Sedra/Smith, 8th edition] The diode has the following current-voltage (i-v) characteristics: [reproduced from Sedra/Smith, 8th edition] Diodes are employed in many day-to-day electronic/electrical systems: To rectify — converting alternating current source (AC) to DC voltage To limit – for waveform shaping restricting operating voltages to values controlled by the diode’ threshold voltage (the voltage at which the diode switched from an open to a short circuit) and to To protect circuits – from high voltages (to direct high voltage signals above the diode’s threshold voltage to ground to protect sensitive amplifier circuits) Limiter (clamper) Limiter circuits are used to 'limit' the voltage levels to predetermined threshold values often employed to restrict voltage levels to safe limits to prevent damage to active components (e.g., input of an OpAmp) Reversing the diode’s polarity will limit the negative output to the diode drop When vI is negative (0.7V), diode is forward biased, and voltage across the diode stays constant; hence output is clipped at +0.7 V When vI is negative, diode is reverse biased and hence OFF àvO = vI (the output voltage is clipped) What is the function of the “crossed diodes” in this circuit? [Carl A Michal 2010 Meas. Sci. Technol. 21 105902], A low-cost spectrometer for NMR measurements in the Earth’s magnetic field. Half-Wave Rectifier The Half-wave rectifier uses a single diode in series with the AC source The rectified voltage is to be fed to a load resistance R1 From our ideal diode description, we can say that During the positive half of sine input, the diode is closed switch During the negative half, the diode acts as an open switch Half-wave rectifier: Output signal The opening and closing of the diode cause current flow only in the positive half of the input sine wave —> the voltage across the load has a single polarity, corresponding to the closed-circuit condition —> one half-cycle of the input-wave is retained, the other is lost Half-wave rectifier: output voltage expression for negative input We analyze the circuit behavior at two half-cycles of input For negative half-cycle of input: 𝑉! (𝑡) < 0𝑉à the diode acts as an open circuit 𝑖" (𝑡) = 0𝐴 à 𝑽𝑶 (𝒕) = 𝟎𝑽 (the voltage across the resistor R1 equals zero) Half-wave rectifier: output voltage expression for positive input 𝑉! (𝑡) ≥ 0𝑉à the diode acts as a short circuit $! (&) 𝑖" (𝑡) ≠ 0𝐴 ; 𝑖" (𝑡) = (" ; @peak voltage: 𝑖! (𝑡 = 0.0625𝑠) = 0.12𝐴 à 𝑽𝑶 (𝒕) = 𝒊𝑫 (𝒕) ∙ 𝑹𝟏 Half-wave rectifier: Output signal analysis I What is the equivalent DC voltage of the output signal? 1 𝑉!,#$ = % 𝑉!,%&' sin(𝜔𝑡)𝑑𝑡 𝑇 ( ( 𝜔 ) = % 𝑉!,%&' sin(𝜔𝑡)𝑑𝑡 2𝜋 * ( 𝜔 −𝑐𝑜𝑠(𝜔𝑡 ) ) = 𝑉!,%&' 1 6 2𝜋 𝜔 * −𝑉!,%&' 𝑉!,%&' = [ ( ) ( )] 𝑐𝑜𝑠 𝜋 − 𝑐𝑜𝑠 0 = = 𝟑. 𝟏𝟖𝑽 2𝜋 𝜋 Half-wave rectifier: Output signal analysis II What is the average output power? 1 ) 𝑃! = %@𝑉!,%&' sin(𝜔𝑡)A 𝑑𝑡 𝑇 ( ( 1 ) = % 𝑉!,%&' ) sin) (𝜔𝑡)𝑑𝑡 𝑇 * ( ) 𝑉!,%&' ) = % [1 − cos(2𝜔𝑡)] 𝑑𝑡 2𝑇 * −𝑉!,%&' 𝑇 𝑉!,%&' ) = = = 𝟐𝟓𝑾 2𝑇 2 4 What is the average input power? ) 1 𝑉+ 𝑃+ = % (𝑉+ sin(𝜔𝑡))) 𝑑𝑡 = = 50𝑊 𝑇 ( 2 What is the output gain? 𝑃! 𝐴, (𝑑𝐵) = 10𝑙𝑜𝑔-* N O = −3𝑑𝐵 𝑃. An attenuation of 3dB (or 0.5 times the input power is dropped over R1) Learning outcomes: You should understand the concept of non-linear circuit elements. You should be able to explain, in words and equations, the diode, and to analyse some circuits containing diodes. You should be able to implement and use diodes in as limiting, protecting, and half wave rectifying circuits.  9 | Analogue to Digital Conversion 2E6-B Objectives: To introduce the Analogue-to-Digital Converter (ADC). To introduce the temporal sampling theorem. To analyse example ADC circuits.  DATA CONVERTERS analogue signals can take on any value from a continuous range, but a digital signal can take on only a finite number of values at discrete and spaced time points, each of which is represented by a digital code. To understand conceptually what is involved, consider the following example. The analogue signal is to be converted to digital form. To do this, it is first sampled in time – i.e. its value is examined at certain time instants, which are indicated in the example by the short vertical lines. All other values of the signal are disregarded. Sampling a continuous-time analogue signal in (a) results in the discrete-time signal in (b) Temporal Resampling/Dwell Time/ Sampling Rate 1Hz analogue signal à T = 1s 𝑑𝑤𝑒𝑙𝑙 𝑡𝑖𝑚𝑒 = 0.05𝑠 1 𝑓! = 𝑠𝑎𝑚𝑝𝑙𝑖𝑛𝑔 𝑟𝑎𝑡𝑒 = = 20𝐻𝑧 𝑑𝑤𝑒𝑙𝑙 𝑡𝑖𝑚𝑒 Q: Haven’t we just lost most of the information about the signal? A: No, the sampling theorem states the following: Sampling Theorem: Any bandlimited signal is completely described by, and can be reconstructed from, the values of uniformly spaced samples taken at a rate greater than twice the signal bandwidth. For a given bandlimited signal with bandwidth B, this minimum sampling rate is called the Nyquist rate, and is equal to 2xBandwidth. This is a property that depends only on the signal itself. For a given sampling rate fs, the maximum frequency content that is allowed in the signal (for which reconstruction is possible) is called the Nyquist frequency, and is equal to fs/2. This is independent of any signal, rather it depends only on the available equipment and the maximum possible sampling rate fs. Q: What happens if the signal has components at frequencies greater than half the sampling frequency? A: We get aliasing, as illustrated next.  VIOLATION of Sampling Theorem: 21Hz analogue signal à T = 0.0476s 1 𝑓! = 𝑠𝑎𝑚𝑝𝑙𝑖𝑛𝑔 𝑟𝑎𝑡𝑒 = = 𝟐𝟎𝑯𝒛 0.05𝑠 à analogue signal at 21Hz creates 1Hz alias signal after sampling (we call this effect aliasing) Q: We now know that the analogue signal must be sampled faster than the Nyquist rate. What happens in the practical case where the signal is not bandlimited? A: We precede our ADC with an anti-aliasing filter – a low-pass filter which blocks all frequency components greater than fs/2. In practice we cannot block these components completely, but we seek to ensure that their effect is negligible. (Note that fs is of course chosen at a value such that all important components of the signal lie at frequencies less than fs/2.) Do not confuse the terms Nyquist rate and Nyquist frequency. MATLAB CODE %plot rotating line y=Vp*sin(2*pi*f*t+phi); x=Vp*cos(2*pi*f*t+phi); subplot(122); clear all; plot(x,y,'-','LineWidth',2);hold on xlabel('imaginary [V]') Vp=10; %V ylabel('real [V]') f=1; %Hz Using a sampling rate of 20Hz set(gca,'FontSize',30); %1Hz anticlockwise rotation grid on; %5Hz frequency preserving anticlockwise rotation %10Hz worst case - DC %15Hz alising, clockwise rotation %% sample signal %20Hz worst case - DC fsampling=20; %21Hz beautiful sinus, heavy alising, anticlockwise rotation %2.6 undersampled - anti clockwise rotation angle=0; %in degrees %0.6 clockwise rotation phi=angle/180*pi; %radians dwelltime=1/fsampling; tsampled=0:dwelltime:1; %s dwelltime=0.0001; ysampled=Vp*sin(2*pi*f*tsampled+phi); fsampling=1/dwelltime; xsampled=Vp*cos(2*pi*f*tsampled+phi); t=0:dwelltime:1; %s for i=2:length(xsampled)-1 V=Vp*sin(2*pi*f*t+phi); subplot(121); figure(1);clf; hDot=plot([ tsampled(i)],[ ysampled(i)],'-ro','LineWidth',2) subplot(121); plot([tsampled(i-1) tsampled(i)],[ysampled(i-1) ysampled(i)],'-r','LineWidth',2) plot(t,V,'LineWidth',2) title(['Sampling rate =' num2str(fsampling) 'Hz']) set(gca,'FontSize',30); legend([hDot],'sampled signal point') xlabel('time [s]') ylim([-15 15]) ylabel('voltage [V]') axis square; grid on;hold on subplot(122);hold on xlim([0 1]) ylim([-12 12]) hSampleLine=plot([0 xsampled(i)],[0 ysampled(i)],'-ro','LineWidth',2) ylim([-15 15]) xlim([-15 15]) axis square; waitforbuttonpress delete(hDot) delete(hSampleLine) end Magnitude Discretisation /Resolution  Sample and Hold Next, we consider how the sampling operates in circuit form. Conceptually, we have the following sample-and-hold circuit: S vo vi C The switch S is operated by a clock signal which closes periodically. When S is closed vo equals vi. When it is open, vo holds its value. This is illustrated below, where S is closed when the clock signal is high, and open when it is low. Between the sampling intervals, i.e. during the hold intervals, the signal samples are available to the ADC for conversion to digital form.  vi(t) t Clock t vo(t) t [O. Feely] Q: How is the switch implemented in practice? A: One possibility is an NMOS (The N-channel metal-oxide semiconductor (NMOS) transistor) transmission gate. [Moritz Klein, “Designing a Samsam and hold circuit from scratch”, YouTube] The NMOS transistor is suitable for this application since it can conduct current in either direction, and since the source and drain voltages do not follow the gate voltage variation. When the gate voltage is low, no current flows and the output voltage remains fixed, provided there is no alternative discharge path for the capacitor. To ensure this, a buffer may be inserted after the capacitor. The capacitor must also have negligible leakage. More complex CMOS (Complementary Metal-Oxide-Semiconductor) switches provide better performance, but at the expense of greater circuit complexity. Note that the sample and hold may be integrated with the ADC, or may be a separate circuit, while some forms of ADC do not need the sample and hold.  Analogue-to-Digital Conversion [Sedra/Smith] Block-diagram representation of the analogue-to-digital converter (ADC). Analogue input is a single numerical value vA, e.g. vA = 5.246V (continuous decimal) This number is converted to the closest resolvable number, e.g. 5 (discrete decimal) The resolved sample number is converted to a binary number, e.g. 101 (binary) (b0=1; b1=0; b2=1) decimal binary 0 000 1 001 2 010 3 011 4 100 5 101 6 110 7 111  FLASH ADC (lightning-fast conversion speed) Returning to our ADC, once the analogue signal has been sampled, the next step is to quantize it. Here, the value of the signal at each of the sampling times is compared to a set of quantization levels – the four dashed lines in the figure below [O. Feely] – and the closest level is selected. This is the process of quantization. Each of the quantization levels is identified by a digital code, and the output is made up by assembling the digital codes corresponding to the quantization levels closest to the signal at each of the sampling instants. Thus, in the example, the analogue signal is converted to the digital representation 01 11 01 00 11 01. The ability of the digital output to provide a good representation of the analogue input depends on the number of quantization levels. This is equal to 2b, where b is the number of bits in the digital code which represents each individual sample. The example above is a 2-bit analogue-to-digital conversion process, which has only 4 levels and so provides very coarse quantization. The larger the number of bits, the better the resolution of the converter (i.e. the smaller the gap between the levels). The difference between the input and the closest reference level to it is the quantization error. There are many terms and acronyms used to quantify the performance of ADCs, and sample and hold circuits. A review of this terminology is presented in the following paper: “Terminology related to the performance of S/H, A/D, and D/A circuits” Tewksbury, S. et al, IEEE Transactions on Circuits and Systems, Volume 25, Issue 7, Jul 1978 pp. 419 – 426. Designers often use the rule of thumb that the signal-to-noise ratio (SNR, whereby noise we mean quantization error here) of an N-bit ADC that operates as outlined above is given by 6.02N + 1.76 dB. This is based on a sinusoidal signal that occupies the full scale of the converter, i.e. with peak-to-peak amplitude 2ND. (D is the difference between two adjacent levels, and we take full scale to be the range of inputs for which the quantization error is £ D/2.) The rms value of the 2N D sinusoid is then 2 2 Assuming the quantization error to be uniformly distributed over the interval [-D /2, D /2], its rms value is 1 D/2 2 D ò x dx = D -D / 2 12 The SNR in dB is then 2N D 12 20 log10 = 6.02N + 1.76 dB 2 2D Many different ADCs are available, of varying speed and complexity. Example 1: The op amps in the following circuit are ideal (infinite gain) with saturation voltages of ±Esat. Find the output voltages vo1, vo2 and vo3 3R vo3 2R vo2 8V 2R vo1 vi R Because the op amps are ideal, they have zero input current. Therefore, the same current flows through all the resistors, and we can apply voltage division to find the voltages at the inverting terminals of the op amps to be (starting from the bottom) 1 V, 3 V and 5 V. Thus vo1 = -Esat when vi < 1 V Esat when vi > 1 V vo2 = -Esat when vi < 3 V Esat when vi > 3 V vo3 = -Esat when vi < 5 V Esat when vi > 5 V If we take the bit 0 to correspond to –Esat, and the bit 1 to correspond to Esat, the outputs can be summarised as follows: vi vo1 vo2 vo3 5V 1 1 1 Each analogue voltage range at the input has been converted into a 3- bit digital word. This form of digital code is known as a thermometer code, since it looks like the mercury bar in a thermometer. Since there are only four possibilities, the 3-bit words can be converted into 2-bit words using straightforward digital logic. Thus, this circuit forms the basis for a 2-bit analogue-to-digital converter. It should be clear that to generalise to a N-bit ADC will require 2N – 1 comparators. (These would not normally be implemented using op amps – this implementation was for the purposes of the example. The symbol generally used for a comparator is the same as that used for the op amp, without the ground terminal.) This circuit is called a parallel or flash ADC since it simultaneously compares the input to a number of reference levels. Flash ADCs are fast but they require a large number of comparators, which take up a large area and are very power hungry. Example 2: You are asked to design a 4-bit flash ADC. How many comparators are required? Design the circuit, using a 10 V reference and 1 kW resistors. Give the output of the comparators and the output of the digital logic for inputs from 0 V to 10 V. What is the resolution of the converter? If a comparison is possible in 50 ns and the associated logic requires 35 ns, what is the maximum possible conversion rate?  15 inputs 4 outputs... digital logic 10 V vi (All resistors 1 kW.) 24 – 1 =15 comparators  111111111111111 1111 011111111111111 1110 output output of comparators of digital logic 000000000000111 0011 000000000000011 0010 000000000000001 0001 000000000000000 0000 0.3125 1.5625 9.0625 0.9375 vi [O. Feely] The resolution of the ADC is 0.625 V. The maximum possible conversion rate is 1/(85 x 10–9) = 11.76 MHz. [Sedra/ Smith, p.15] Learning outcomes: You should understand the concept of the Analogue-to-Digital Converter (ADC). You should be able to explain, in words and equations, the temporal sampling theorem. You should be able to implement and use an ADC as part of circuits.  8 | Cascading 2E6-B Objectives: To introduce the cascade of multiple op-amps. To analyse some circuits containing cascades. What if you need more gain? A single linear amplifier provides sufficient gain for many applications typically, a gain of 100 to 100 000 in many cases However, in some cases, the signal is too small some sensors produce excitation in the range of pA’s Amplifying the signal using a single device might not be feasible cascading multiple stages? What if you need more gain? Chain together stages of linear amplifiers Output of first amplifier goes to input of 2nd amplifier Output of 2nd amplifier goes to input of 3rd and so on.. Cascade as many number of stages as needed Usually, a system of K (≥ 2) stages Voltage-controlled Voltage-controlled voltage source voltage source Equivalent circuit For a system of K = 2 stages, we get Input fed through voltage division into the first amplifier ( ) The first stage produces an 𝑉!,# (𝑡) = 𝐴$#! × 𝑉',# (𝑡) Divided among the output and input of second stage ( ) Scaled up to 𝑉!,( (𝑡) = 𝐴$(! × 𝑉',( (𝑡) Voltage-controlled Voltage-controlled voltage source voltage source Stage - 1 marked by superscript Stage - 2 marked by superscript (1) (2) Equivalent circuit Output of the first stage of amplifier is given by ( ) ( ) 𝑉! # (𝑡) = 𝐴$#! × 𝑉' (𝑡) This passes through the potential divider between the 2 stages to form input at stage 2 ($) ($) (() )" (#) )" (#) i.e., 𝑉' (𝑡) = ( $) (&) × 𝑉! = ($ ) ( &) × 𝐴$! × 𝑉' (𝑡) )" *)! )" *)! Voltage-controlled Voltage-controlled voltage source voltage source Stage - 1 marked by superscript Stage - 2 marked by superscript (1) (2) Equivalent circuit Output of the second stage of amplifier is given by The final voltage at the load is thus ( ) ( ) ( ) i.e., 𝑉! ( (𝑡) = 𝐴$(! × 𝑉' ( (𝑡) ( ) (() (() 𝑅' ( (# ) 𝑉! (𝑡) = 𝐴$! × ( ) ( ) × 𝐴$! × 𝑉' (𝑡) 𝑅' ( + 𝑅!# The final voltage at the load is thus )' ( ) 𝑉! ( Voltage-controlled Voltage-controlled i.e., 𝑉+ = × voltage source voltage source ( $) )' *)! Stage - 1 marked by superscript Stage - 2 marked by superscript (1) (2) Equivalent circuit Putting it all together, we get system gain as ( #) (( ) 𝑅' 𝑅' 𝑅+ ( ) ( ) 𝐴$( = ( #) × ( ) ( () × ( ) × 𝐴$#! × 𝐴$(! 𝑅, + 𝑅' 𝑅!# + 𝑅' 𝑅!( + 𝑅+ or in decibels (") (() 𝑅$ 𝑅$ 𝑅* (") (() 𝐴!! [𝑑𝐵] = 20𝑙𝑜𝑔"# - (") 0 + 20𝑙𝑜𝑔"# - (") (() 0 + 20𝑙𝑜𝑔"# 1 (() 2 + 𝐴!" [𝑑𝐵] + 𝐴!" [𝑑𝐵 ] 𝑅' + 𝑅$ 𝑅) + 𝑅$ 𝑅) + 𝑅* i.e., sum of gains - sum of attenuations Voltage-controlled Voltage-controlled voltage source voltage source Stage - 1 marked by superscript Stage - 2 marked by superscript (1) (2) Example: Available to you are several voltage amplifiers, all identical, with the following parameters: 𝑅' = 1𝑘Ω, 𝑅! = 20Ω, 𝐴$! = 34𝑑𝐵. The circuit has the following terminations at source and load: 𝑅- = 100Ω, 𝑅+ = 1.2𝑘Ω. Determine the cascading that can provide a net voltage gain between source and load of 120 dB. Solution: Let there be 𝐾(≥ 2) stages: Using the gain equation, 𝐴!# = 𝐺𝑎𝑖𝑛 𝑜𝑓 𝐾 𝑠𝑡𝑎𝑔𝑒𝑠 + 𝑠𝑜𝑢𝑟𝑐𝑒 𝑎𝑡𝑡𝑒𝑛𝑢𝑎𝑡𝑖𝑜𝑛 + 𝑙𝑜𝑎𝑑 𝑎𝑡𝑡𝑒𝑛𝑢𝑎𝑡𝑖𝑜𝑛 + 𝑎𝑡𝑡𝑒𝑛𝑢𝑎𝑡𝑖𝑜𝑛 𝑏𝑒𝑡𝑤𝑒𝑒𝑛 𝐾 𝑠𝑡𝑎𝑔𝑒𝑠 (") (() 𝑅$ 𝑅$ 𝑅* (") (() 𝐴!! [𝑑𝐵] = 20𝑙𝑜𝑔"# - (") 0 + 20𝑙𝑜𝑔"# - (") (() 0 + 20𝑙𝑜𝑔"# 1 (() 2 + 𝐴!" [𝑑𝐵 ] + 𝐴!" [𝑑𝐵 ] 𝑅' + 𝑅$ 𝑅) + 𝑅$ 𝑅) + 𝑅* 1000Ω 1000Ω 1200Ω 𝐴!! [𝑑𝐵] = 20𝑙𝑜𝑔"# 5 9 + (𝐾 − 1) × 20𝑙𝑜𝑔"# 5 9 + 20𝑙𝑜𝑔"# 5 9 + 34𝑑𝐵 × 𝐾 100Ω + 1000Ω 20Ω + 1000Ω 20Ω + 1200Ω Given, we need 𝐴! [𝑑𝐵] ≥ 120𝑑𝐵 ! à 120𝑑𝐵 ≤ −0.83𝑑𝐵 + (𝐾 − 1) × (−0.17𝑑𝐵) − 0.14𝑑𝐵 + 34𝑑𝐵 × 𝐾 121.14𝑑𝐵 ≤ (34𝑑𝐵 − 0.17𝑑𝐵) × 𝐾 121.14𝑑𝐵 ≤ (33.83𝑑𝐵) × 𝐾 3.58 ≤ 𝐾 i.e., Minimum of 4 stages required to achieve gain of 120 dB Non-ideal behaviour Voltage amplifiers are not ideal devices non-linear across the entire operating range Think of resistors — current flow —> the energy dissipated as heat —> changes the resistance Non-ideal nature of devices are caused by numerous factors Atomic impurities, variations in fabrication, fluctuations in Vcc Non-ideal nature the linear operating transfer characteristics is not true Non-ideal transfer characteristics non-linear characteristics Operating/Dynamic Range The shape is “S” like —> there is a very small part of the curve where the amplification can be approximated to linear Impact of non-linearity Non-linear characteristics introduces distortions to the amplified signal The output signal has a different amplitude to the linear amplifier Output has same period, T and broadly follows the same repetitive shape as the output of an ideal amplifier We will see that the distortions are better understood by observing the frequency domain, for which we will utilise a tool from mathematics - Fourier Series 10V t T VEVOX: what circuit components do you recognize in this circuit? [Carl A Michal 2010 Meas. Sci. Technol. 21 105902], A low-cost spectrometer for NMR measurements in the Earth’s magnetic field. Cross-section through water bottle with 70mm diameter. Magnetic Resonance Image captured using the Earth Field MRI scanner with 4x4x20mm voxel resolution in 180mins acquisition time. Learning outcomes: You should understand the concept of cascading of amplifiers. You should be able to explain, in words and equations, how cascading of op-amp works. You should be able to implement and use cascaded op-amps in circuits. Recall: Summing amplifier An extension of the inverting amplifier configuration Instead of single input, feed multiple inputs through individual input resistors Within the operating range, the circuit is linear — the inputs superimpose One of the key applications is a digital to analogue converter (DAC) I/O relation To derive the i/o relation, we apply superposition with individual input conditions, we get (with 𝑖! , 𝑖" = 0𝐴) &!,# &$,# '% 𝑖#," + 𝑖% = 0𝐴 à '# =− '% à 𝑉(," = − ' 𝑉#," , with 𝑉#,! = 𝑉#,) = 0𝑉 # &!,& &$,& ' 𝑖#,! + 𝑖% = 0𝐴 à '& =− '% à 𝑉(,! = − '% 𝑉#,! , with 𝑉#," = 𝑉#,) = 0𝑉 & &!,' &$,' ' 𝑖#,) + 𝑖% = 0𝐴 à '' =− '% à 𝑉(,) = − '% 𝑉#,) , with 𝑉#," = 𝑉#,! = 0𝑉 & Thus, the output when all inputs are applied simultaneously is 𝑉( (𝑡) = 𝑉(," (𝑡) + 𝑉(,! (𝑡) + 𝑉(,) (𝑡) 𝑅% 𝑅% 𝑅% 𝑉( (𝑡) = − 𝑉#," + − 𝑉#,! + − 𝑉#,) 𝑅" 𝑅! 𝑅! or in general for n inputs, 𝑅% 𝑅% 𝑅% 𝑅% 𝑉( (𝑡) = − 𝑉#," − 𝑉#,! − 𝑉#,) + ⋯ − 𝑉#,* 𝑅" 𝑅" 𝑅" 𝑅* Digital to Analogue conversion (DAC) We have the I/O relation 𝑅% 𝑅% 𝑅% 𝑅% 𝑉( (𝑡) = − 𝑉#," − 𝑉#,! − 𝑉#,) + ⋯ − 𝑉#,* 𝑅" 𝑅! 𝑅! 𝑅* Consider that each of these input voltages represent the bits in a binary word 𝑊 = 𝑏*+" 𝑏*+! 𝑏*+) … 𝑏! 𝑏" 𝑏, , 𝑏𝜖 {0,1} The analogue equivalent voltage is thus the sum of each position multiplied by its positional weight i.e., analogue equivalent of 𝑊 = 2*+" × 𝑏*+" + 2*+! × 𝑏*+! + ⋯ + 2! × 𝑏! + 2" × 𝑏" + 2, × 𝑏,  𝑊 = 𝑏*+" 𝑏*+! 𝑏*+) … 𝑏! 𝑏" 𝑏, , 𝑏𝜖 {0,1} i.e., analogue equivalent of 𝑊 = 2*+" × 𝑏*+" + 2*+! × 𝑏*+! + ⋯ + 2! × 𝑏! + 2" × 𝑏" + 2, × 𝑏, Thus, by choosing appropriate 𝑹𝟏 … 𝑹𝒏 , we can achieve this conversion: ' ' ' e.g., 𝑅% = 𝑅 à 𝑅, = 𝑅, 𝑅" = ! , 𝑅! = !& ,… 𝑅*+" = !()# 𝑏, 𝑏" 𝑏*+" 𝑊0(123 = −(2, 𝑏, + 2" 𝑏" + ⋯ + 2*+" 𝑏*+" ) Vevox: DAC circuit How do we have to connect the Op-Amps to the circuit to achieve the provided input/output function of a Digital to Analogue Converter (DAC)?  7 | Voltage Controlled-Voltage Source 2E6-B Objectives: To introduce the voltage-controlled voltage source. To establish real world limitations of the ideal op-amp conditions. To analyse some circuits containing voltage-controlled voltage sources. Recall: Single-input single-output (SISO) amplifier Voltage amplifier — an active device with typically high voltage and power gains Active — it constantly draws energy from an external source Takes one signal as input and produces a single output signal Operating Range: Specifies the range of input for which the device acts as linear amplifier Operating Range Linear transfer characteristics can be represented as Operating/Dynamic Range For an input signal within the operating range, an ideal amplifier —> a linear device scaling the input signal by the gain of the device 𝑉(24524 (𝑡) = 𝐴 ∙ 𝑉#*524 (𝑡), where, A is the ‘open-loop’ voltage gain Non-idealities Even with ideal voltage amplifier, external circuits can introduce non- idealities à Non-idealities associated with source/input and load/output impedances Specifically: 1. A non-ideal voltage source connected to the input 2. The output gain limited by the finite load resistor These create two different conditions: 𝑉# (𝑡) < 𝑉6 (𝑡): i.e., input at pin of amplifier < source voltage 𝑉7 (𝑡) < 𝑉( (𝑡): i.e., voltage at load < the open circuit output Voltage Additionally, the amplifier itself may be non-ideal Finite input and output resistance (i.e, 𝑅# ≠ ∞, 𝑅( ≠ 0Ω ) Finite open circuit (or open-loop) voltage gain (i.e., 𝐴&$ ≠ ∞) We can model both imperfections: Potential dividers at the input and output of the amplifier Equivalent circuit model for this non-ideal linear voltage using input/output resistances Ri → input resistance of the amplifier Ro → output resistance of the amplifier AVo → open-circuit voltage gain of the amplifier  Voltage-controlled voltage source Load or Equivalent circuit of the non- termination ideal voltage amplifier Non-ideal voltage source The 3 parameters Ri, Ro, AVo are associated with non-ideal voltage amplifiers Nominal open-circuit voltage gain of AVo Two resistive elements that attenuate the signal at input and output Ri, and Ro  Voltage-controlled voltage source Based on these parameters Ri, Ro, AVo we can define the I/O relations as: Equivalent circuit of the non- Load or termination '! 𝑉# (𝑡) = × 𝑉6 (Non-ideal '! 8'* 𝑡) voltage source 𝑉( (𝑡) = 𝐴ideal &$ × 𝑉# (𝑡 ) voltage amplifier ' + '+ 𝑉7 (𝑡) = 𝑉( (𝑡) × ' 8' = 𝐴&$ × 𝑉# (𝑡) × ' 8' + $ + $ 𝑅# 𝑅7 𝑉7 (𝑡) = 𝐴&$ × × 𝑉6 (𝑡) × 𝑅# + 𝑅6 𝑅7 + 𝑅( '! '+ 𝑉7 (𝑡) = 𝐴&* × 𝑉6 (𝑡), where 𝐴&* = 𝐴&$ × ' 8' × ' 8' ! * + $  Voltage gain Gain can be expressed in decibels (dB) to indicate the level of power amplification 𝐴&* [𝑑𝐵] = 20𝑙𝑜𝑔", G𝐴&* H, in units of dB 𝑅# 𝑅7 𝐴&* [𝑑𝐵] = 20𝑙𝑜𝑔", G𝐴&$ H + 20𝑙𝑜𝑔", 9 : + 20𝑙𝑜𝑔", 9 : 𝑅# + 𝑅6 𝑅7 + 𝑅( Voltage-controlled voltage source Load or Equivalent circuit of the non- termination ideal voltage amplifier Non-ideal voltage source i.e., Gain is provided by the open loop voltage gain, while the input and output resistances cause attenuation (i.e., negative gain).  Voltage-controlled voltage source Current Gain # # 𝐴9* = #+ = #+ , ! * where & 𝑖6 = * '* 8'! and Load or 𝑉# Equivalent circuit of the non- termination 𝑖7 = 𝐴&$ ideal voltage amplifier Non-ideal voltage source 𝑅( + 𝑅7 &! &* +" &! '* 8'! 𝐴9* = 𝐴&$ ' 8' × I' 8' J = 𝐴&$ ' 8' × &* $ + * ! $ + 𝑅6 + 𝑅# 𝑉# 𝑅6 + 𝑅# 𝑅# 𝑹𝒊 𝐴9* = 𝐴&$ × = 𝐴&$ × = 𝑨𝑽𝒐 𝑅( + 𝑅7 𝑉6 𝑅( + 𝑅7 𝑅6 + 𝑅# 𝑹𝒐 + 𝑹𝑳 Power gain Power gain with respect to input the amplifier can be computed as >+ & # 𝐴>! = >! = &+ × #+ = 𝐴&! 𝐴9! , ! * Voltage-controlled voltage source Load or Equivalent circuit of the non- termination ideal voltage amplifier Non-ideal voltage source Power gain Similarly, power gain can be computed with reference to the source 𝐴>* = 𝐴&* 𝐴9* '! '+ '! 𝐴>* = 𝐴&* 𝐴9* , with 𝐴&* = 𝐴&$ × '! 8'* × '+ 8'$ and 𝐴9* = 𝐴&$ × '$ 8'+ 𝑅# 𝑅7 𝑅# 𝐴>* = 𝐴&$ × × × 𝐴&$ × 𝑅# + 𝑅6 𝑅7 + 𝑅( 𝑅( + 𝑅7 ! ! 𝑅 # 𝑅7 = 𝐴&$ × (𝑅# + 𝑅6 )(𝑅7 + 𝑅( )! Voltage-controlled voltage source Load or Equivalent circuit of the non- termination ideal voltage amplifier Example: A voltage source of 1.3 V rms and internal resistance 50 Ohm is connected to the input of an ideal amplifier. The voltage across the input drops to 1.1 V rms. With no load connected to the output (i.e., open circuit), the voltage at the output of the amplifier is 220 V. When the output is terminated by a 1 kOhm load, the output drops to 170 V. Evaluate the amplifier parameters and quote the voltage, current and power gains with reference to the source.  Solution: Give: at input side: 𝐴6 = 1.3𝑉𝑟𝑚𝑠, 𝑅6 = 50Ω, 𝑉# = 1.1𝑉𝑟𝑚𝑠 '! "."&AB? 𝑉? ⟶ 𝑉# , when input connected ' = ".)&AB? 𝑤𝑖𝑡ℎ 𝑅6 = 50Ω * 8'! 1.3𝑉𝑟𝑚𝑠 × 𝑅# = 1.1𝑉𝑟𝑚𝑠 × (50Ω + 𝑅# ) (1.1𝑉𝑟𝑚𝑠 × 50Ω) 1.1𝑉𝑟𝑚𝑠 × 𝑅# 𝑅# = + 1.3𝑉𝑟𝑚𝑠 1.3𝑉𝑟𝑚𝑠 (1.1𝑉𝑟𝑚𝑠 × 50Ω) 𝑅# − 0.8462𝑅# = 1.3𝑉𝑟𝑚𝑠 (1.1𝑉𝑟𝑚𝑠 × 50Ω) 𝑅# (1 − 0.8462) = 1.3𝑉𝑟𝑚𝑠 (1.1𝑉𝑟𝑚𝑠 × 50Ω) Voltage-controlled 𝑅# (0.1538) = 1.3𝑉𝑟𝑚𝑠 voltage source (1.1𝑉𝑟𝑚𝑠 × 50Ω) 𝑅# = = 275Ω 1.3𝑉𝑟𝑚𝑠 × 0.1538 Load or Equivalent circuit of the non- termination ideal voltage amplifier Non-ideal voltage source Give: at input side: 𝑉( = 220𝑉, 𝑅7 = 1𝑘Ω, 𝑉7 = 120𝑉 '+ "C,& 𝑉( ⟶ 𝑉7 , when output connected = '$ 8'+ 𝑤𝑖𝑡ℎ 𝑅6 = 1000Ω !!,& 1000Ω 170𝑉 = 𝑅( + 1000Ω 220𝑉 1000Ω × 220𝑉 = 𝑅( + 1000Ω 170𝑉 1000Ω × 220𝑉 𝑅( = − 1000Ω = 294.1Ω 170𝑉 Finally, 𝐴&- =220/1.1=200 Complete 𝐴&. , 𝐴9. using the expressions. Recall the ideal amplifier parameters 𝑅# ↑ ∞, and 𝑅( ↑ 0 à 𝐴&$ = 𝐴&* As the name suggests, unity gain means 𝐴&$ = 1 But why would you need an amplifier with unity gain? Recall the direct connection of non-ideal source and low impedance load results in voltage division: i.e.: '+ 𝑉7 = ' × 𝑉6 ≪ 𝑉6 since 𝑅7 ≪ 𝑅6 $ 8'+ Using an ideal UGB in the path eliminates this voltage division 𝑅# ↑ ∞, and 𝑅( ↑ 0 à 𝐴&$ = 𝐴&* = 1 à 𝑉7 = 𝑉6 Also means that the power gain is 1 Recall that a direct connection of non-ideal source to a low impedance load causes attenuation at output (voltage division) /&* /& + & > 0+ 0+ Hence, 𝐴>* = >+ = /& = /& at MPT (max power transmission) * * * 0* 10+ 0* 10+ /& + > 20+ Simplify further at MPT, 𝐴>* = >+ = /& = 0.5 * * &0+ à a minimum attenuation of 50% power Thus, an ideal UGB 1. Eliminates voltage division caused by source/load resistances 2. Eliminates power loss caused – entire power is transferred from source to load 3. At the expense of additional power consumption – active device Learning outcomes: You should understand the concept of the voltage-controlled voltage source. You should be able to explain, in words and equations, real world limitations of the ideal op-amp conditions. You should be able to implement and use voltage-controlled voltage source in circuits.  5 | Practical op-amp circuits 2E6-B Objectives: To introduce the inverting and non-inverting operation amplifier. To establish a stepwise approach to analysing op-amp circuits. To analyse some circuits containing op-amps. Practical Op-Amp circuits To ensure that the Op-Amp provides useful functionality, its operation must be confined to the linear operating range To reduce the high open-loop gain, a feedback path is created from output to input Feedback must be negative — hence always connected to inverting input Practical Op-Amp circuits Op-Amp still amplifies the difference at the input pins i.e., 𝑉! (𝑡) = 𝐴"! × 𝑒# with 𝑉! (𝑡)𝜀 (−𝑉$$ , +𝑉$$ ) %""" '""" à 𝑒# 𝜀 - & , &. #! #! à 𝑒# 𝜀(≈ 0, ≈ 0) But 𝑒# = 𝑒( − 𝑒) à 𝑒) ≈ 𝑒( - (1) in closed loop configuration Practical Op-Amp circuits recall that in case of ideal Op-Amps, the input impedance is taken as infinite Practical Op-Amps also have very high input impedance no current flows into the input pins i.e., 𝑖) = 𝑖( = 0𝐴 — (2) input impedance is very large These 2 equations form the basis for analysing closed-loop Op-Amp configurations Note: The functionality achieved is entirely determined by the external circuitry  The inverting Op-Amp Produces an amplified version of the input with a 180° phase inversion Input into the inverting pin (through a resistor), non-inverting input connected to ground Equivalent circuit of an inverting op-amp.  The gain A is very large (ideally infinite). à if that is “working” and the output is finite, then the voltage difference at the input must be very small. *! 𝑣( − 𝑣) = & = 0𝑉 Analysis concept for an inverting op-amp.  The input at the inverting input is given by 𝑣( = 𝑣) , because A approaches infinity, both input voltage ideally equals each other. The two input terminals are “tracking each other in potential”. This is also referred to as a “virtual short circuit” that exists between two terminals. Note: the two inputs are not physically shortened! A virtual short circuit means that whenever voltage is at 2 will automatically appear at 1 because of the infinite gain A. But Terminal 2 happens to be connected to ground; thus 𝑣( = 0𝑉 and v) = 0V. We speak of terminal 1 as being a virtual ground – being zero voltage without being connected to ground physically. Analysis concept for an inverting op-amp.  Apply Ohm’s law: 𝑣) − 𝑣( 𝑣) − 0𝑉 𝑣) 𝑖) = = = 𝑅) 𝑅) 𝑅) Analysis concept for an inverting op-amp.  Where will this current go: It cannot go into the Op-Amp as it has an infinite resistance and no current ever flows into it. 𝑖+,*-./0,1+,23/ = 0𝐴 Analysis concept for an inverting op-amp.  Therefore, the current must flow through R2 to the low impedance output terminal 3. Applying KCL and connecting the input voltage: 𝑣) 𝑖( = 𝑖) = 𝑅) Analysis concept for an inverting op-amp.  We apply KVL and Ohm’s law to R2 to determine the output voltage: 𝑣! = 𝑣) − 𝑖) 𝑅( 𝑣) 𝑣! = 0𝑉 − 𝑅( 𝑅) CLOSED LOOP GAIN OF AN INVERTING AMPLIFIER. 𝑹𝟐 𝒗𝒐 = − 𝒗𝟏 𝑹𝟏 The transfer function has a negative slope - R2/R1. Equivalent circuit of an inverting op-amp. Unity Gain Buffer (UGB) or impedance transformer The simplest closed-loop Op-Amp circuit Feedback impedance is a short circuit, input fed to non-inverting pin of Op-Amp Output follows input, with unity gain Application: isolates source from load (ideal Op-Amp) 𝑅0 ↑ ∞ à 𝑖( = 𝑖) = 0𝐴 à no voltage division at source further𝑅! ↑ 0Ω à 𝑉! is invariant with load impedance (e.g. during ECG we desire no current flow from the body into the circuitry, this condition achieves that ideally) Unity Gain Buffer (UGB) or impedance transformer Derive input/output relationship: Equation 1 is sufficient in this case: 𝑒# = 𝑒( − 𝑒) à 𝑒) ≈ 𝑒( "! (/) 𝑒) = 𝑒( à 𝑉0 (𝑡) = 𝑉! (𝑡) à 𝐴" = " (/) = 1 $ Linear transfer function with slope 1 Voltage Follower/Impedance Transformer/Unity Gain Buffer Non-inverting amplifier configuration Looks like an inverting amplifier, but has: 1. the input voltage supplied to the non-inverting input, and 2. the inverting input is connected to ground Produces an amplified version of the input with a 0° phase inversion Input into the non-inverting pin (through a resistor), inverting input connected to ground Non-inverting amplifier configuration Derive input/output relationship: Apply KCL at inverting input: 𝑖9 + (−𝑖) ) + 𝑖0 = 0𝐴, 𝑤𝑖𝑡ℎ 𝑖) = 0𝐴 𝑉! (𝑡) − 𝑒) 0𝑉 − 𝑒) + 0𝐴 + = 0𝐴 𝑅9 𝑅0 "! (/)%"$ (/) ;"%"$ (/) : + 0𝐴 + : = 0𝐴 , with 𝑒) = 𝑒( = 𝑉0 (𝑡 ) % $ 𝑉! (𝑡) − 𝑉0 (𝑡) 𝑉0 (𝑡) − = 0𝐴 𝑅9 𝑅0 𝑉! (𝑡) 𝑉0 (𝑡) 𝑉0 (𝑡) − − = 0𝐴 𝑅9 𝑅9 𝑅0 𝑉! (𝑡) 𝑉0 (𝑡) 𝑉0 (𝑡) = + 𝑅9 𝑅9 𝑅0 𝑉0 (𝑡) 𝑉0 (𝑡) 𝑅9 𝑉0 (𝑡) 𝑹𝑭 𝑉! (𝑡) = 𝑅9 D + E = 𝑉0 (𝑡) + = 𝑉0 (𝑡) -𝟏 +. 𝑅9 𝑅0 𝑅0 𝑹𝒊 Non-inverting amplifier configuration Input/output relationship: 𝑉! (𝑡) 𝑹𝑭 𝐴𝑧" = = -𝟏 +. 𝑉0 (𝑡) 𝑹𝒊 As with inverting amplifier, gain depends on the feedback and put resistors No phase inversion as the gain is positive Transfer function: A linear transfer function with positive slope Output saturates when 𝑉! ≥ 𝑉$$ Example: An application requires an input voltage to be amplified to a gain of 40 dB for processing requirements. Design a linear amplifier for this task. State assumptions if any. Example: An application requires an input voltage to be amplified to a gain of 40 dB for processing requirements. Design a linear amplifier for this task. State assumptions if any. Soln: Since gain required with no phase shift, we need a non-inverting configuration. Given 𝐴" (𝑑𝐵) = 20𝑙𝑜𝑔); (𝐴" ) = 40𝑑𝐵 à 𝐴" = 100 :% i.e., P1 + : Q = 100 à 𝑅9 = 99 × 𝑅0 (non-inverting op-amp) $ Let 𝑹𝒊 = 𝟏𝟎𝟎𝛀 à 𝑹𝑭 = 𝟗. 𝟗𝒌𝛀 Assumption: Ideal non-inverting Op-Amp assumed, with input within the operating range Learning outcomes: You should understand the concept of the buffering, inverting, and non- inverting amplifiers. You should be able to explain, in words and equations, those op-amp circuits. You should be able to implement and use op-amps in those circuits.  4 | The op-amp 2E6-B Objectives: To introduce the concept of amplification. To introduce how amplification factors are converted into units of decibel. To introduce the ideal op-amp and to establish the two ideal conditions of op-amps. Single-input single-output amplifier Voltage amplifier — an active device with typically high voltage and power gains Active — it constantly draws energy from an external source usually a dual-rail supply of the form Takes one signal as input and produces a single output signal Voltage Gain Specifies the range of input for which the device acts as described, i.e., range of inputs for which the device functions as an amplifier For an input signal within the operating range, An ideal amplifier —> a linear device scaling the input signal by the gain of the device 𝑉!"#$"# (𝑡) = 𝐴 ∙ 𝑉%&$"# (𝑡) where, A is the ‘open-loop’ voltage gain Gain Factor in decibel e.g., A = 100 à the output voltage will be a 100 times the input signal Because we consider amplification factors in multiples of ten (ranging from 10 to 100000) we conveniently use the gain factor measured in units of decibel (dB) 𝑉!"#$"# 𝐴[𝑑𝐵] = 20 ∙ 𝑙𝑜𝑔'( = 40𝑑𝐵 𝑉%&$"# Amplification factor 1 2 10 100 1000 10000 [Vo/Vi] Amplification factor 0 6 20 40 60 80 [20log10(Vo/Vi) dB] Power Gain Power gain is defined as 𝑃!"#$"# (𝑡) = 𝐴) ∙ 𝑃%&$"# (𝑡) % % *!"#$"# *!"#$"# 𝑃!"#$"# = + = ', , note R = 1Ohm assumed in ideal conditions - 𝑃!"#$"# 𝑉!"#$"# 𝑽𝒐𝒖𝒕𝒑𝒖𝒕 𝐴) [𝑑𝐵] = 10 ∙ 𝑙𝑜𝑔'( = 10 ∙ 𝑙𝑜𝑔'( - = 𝟐𝟎 ∙ 𝒍𝒐𝒈𝟏𝟎 𝑃%&$"# 𝑉%&$"# 𝑽𝒊𝒏𝒑𝒖𝒕 𝐴)!678 = 𝐀𝟐𝑽𝒐𝒍𝒕𝒂𝒈𝒆 Operating Range Transfer characteristics can be represented as Operating/Dynamic Range Output signal distortion Consider a random information-bearing signal e.g., EEG signal from the sensors Typical signal amplitudes in the range 𝑉?@A = ±100𝑚𝑉 Before processing, this signal is amplified with one or more stages of amplifier Let the amplifier be powered by a DC external supply ±𝑉BB Assume the configured voltage gain is 𝐴* Vi(t) t Output signal distortion If |𝐴* ∙ 𝑉?@A | < 𝑉BB the amplified signal is within the operating range The output of an ideal voltage amplifier produces a power- boosted representation of the input EEG signal with no distortion Vo(t) t Output signal distortion Conversely, if the input signal is outside the operating range, then the signal gets clipped at the rail limits. Consider a sine input with zero mean and a peak voltage Vp of 150 mV. Amplifier operating on ±12𝑉 dual-rail supply voltage with a voltage gain 𝐴* of 100 à The peak output voltage |𝐴* ∙ 𝑉?@A | = 15𝑉 > 𝑉BB 0.15V t T Output signal distortion The output signal gets symmetrically clipped at ±𝑉BB t T Amplitude distortion since only amplitude of the output is affected Other possible parameters could be affected — phase, wave-shape, frequency (or a combination of these) Operational Amplifiers or Op-Amps: Unlike SISO amplifiers we have seen so far, Op-Amps are A 2 input, 1 output amplifier Differential amplifier provides a near-ideal gain performance Output is the amplified version of the difference between inputs 𝐴* is called the open-loop gain of the Op-Amp Ideal Op-Amps 2 inputs: inverting (-) and non-inverting (+) Ideal condition 1: Very high input resistance/impedance (↑ ∞) à i1 = i2 = 0A , hence no voltage drop at input à e1 = VS1 and e2 = VS2  Ideal condition 2: Very high open loop voltage gain In the order of 104,105, ideally 𝐴* ↑ ∞ Ideal Op-Amps: Transfer function Based on ideal conditions, we can derive the I/O characteristics as Slope is called slew-rate when difference input is positive, output saturates at +𝑉BB when difference input is negative, output saturates at −𝑉BB Not very useful in real-world (other than as comparators) Ideal Op-Amps in Open-loop As mentioned, open-loop op-amp configuration can be employed as comparators When 𝑒' > 𝑒- , 𝑉! = −𝑉{BB} When 𝑒' < 𝑒- , 𝑉! = +𝑉{BB} binarised output signal (one of 2 levels) e.g. application: difference signals among sensors  Ideal condition 1: Very high input resistance/impedance (↑ ∞) à i1 = i2 = 0A Ideal condition 2: Very high open loop voltage gain Learning outcomes: You should understand the concept of amplification. You should be able to explain, in words and equations, amplification factors, and to convert amplification factors to units of decibel. You should be able to recall and apply the two ideal op-amp conditions.  3 | The full wave rectifier 2E6-B Objectives: To introduce the concept of the filtering capacitor. To introduce the full wave rectifier. To analyse the output function with regards to root mean square voltages, average power, and power gain. Block diagram of a power supply converting an alternating current (AC) into a direct current (DC) [reproduced from Sedra/Smith, 8 edition] th When we replace the load resistance with a capacitance the alternating input voltage converts into a constant output voltage. The capacitor retains its voltage because there is no way for it to discharge. More practically we will have to connect a load in parallel to the capacitor. With the initially positive voltage (assuming an ideal diode) the diode opens and the capacitor charges. With a negative voltage across the diode the capacitor discharges across the resistor. Circuit analysis under the assumption CR>>T, where T is the period of the input sinusoidal signal (0.25ms). "! Load current: 𝑖! = #" &"# Diode current (when open): 𝑖$ = 𝑖% + 𝑖! = 𝐶 ∙ &' + 𝑖!  Peak to Ripple voltage: Vp2r Conduction interval: Dt 1. The diode conducts for a brief interval, Dt, near the peak of the input sinusoid and supplies the capacitor with charge equal to that lost during the much longer discharge interval. The latter is approximately equal to the period T. 2. The discharge happens at a time constant RC during T. During the diode-off interval, the output voltage can be expressed as: ' * 𝑣( = 𝑣) 𝑒 %# 3. The peak to ripple voltage can be computed as: , * 𝑣+ ~𝑣) 𝑒 %# The full-wave rectifier circuit: [plotted and simulated using MultiSim Live] A transformer with turns-ratio n:2n is used —> output voltage between the outer taps is twice the input A central tap which divides the output is employed as reference ground Voltage between any of the outer taps and the centre-tap ground is of opposite polarity During positive half-cycle of input: Forward biased D2 conducts current through to R1 Current flows from upper tap through D2, into R1 and to ground (i.e., to central tap) to complete the circuit Peak output voltage is the same as the input voltage 𝑉- (𝑡) ≥ 0𝑉 à D2 is closed, D1 is open 𝑉( (𝑡) = 𝑉- (𝑡) = 𝑉. sin 𝜔𝑡 During negative half-cycle of input: Forward biased D1 conducts current through to R1 Current flows from lower tap through D1, into R1 and to ground (i.e., to central tap) to complete the circuit Peak output voltage is the inverse of the input voltage 𝑉- (𝑡) < 0𝑉 à D2 is open, D1 is closed 𝑉( (𝑡) = −𝑉- (𝑡) = −𝑉. sin 𝜔𝑡 Full-wave rectifier: Output signal analysis Average output power Recall that the output is periodic with period T/2 , , 𝟐 2 / 𝑉./ / 𝑽𝑺 𝑃( = 8 𝑉./ sin/ 𝜔𝑡 𝑑𝑡 = 8 (1 − cos 2𝜔𝑡) 𝑑𝑡 = 𝑇 0 𝑇 0 𝟐 Average power injected , / 4$% 𝑃3 = ∫0 𝑉3 (𝑡)𝑑𝑡 = / à 𝑃( = 𝑃3 or unity power gain (0dB) The effect of power loss in source impendence is avoided. Design considerations to smoothen the rectifier output: time constant tau=CR >> discharge interval (~T). Learning outcomes: You should understand the concept of the filtering capacitor. You should be able to explain, in words and equations, the full wave rectifier. You should be able to implement and use transformer, diodes, and capacitors to achieve AC to DC conversion.