Lecture 2.pptx

Faculty of Computing and Informatics Top-level view of Computer function and interconnections Faculty of Computing and Informatics Objectives of the Lecture:-  Computer components  Computer function  Interconnection structures  Bus interconnection  Point-to-point interconnection ...

Faculty of Computing and Informatics Top-level view of Computer function and interconnections Faculty of Computing and Informatics Objectives of the Lecture:-  Computer components  Computer function  Interconnection structures  Bus interconnection  Point-to-point interconnection  PCI Express Lecture Objectives At the end of this lecture, we should be able to:-  Describe the concept of interconnection within a computer system.  Explain the need for multiple buses arranged in hierarchy.  Assess the relative advantages of point-to-point interconnection compared to bus interconnection.  Present an overview of PCIe. + Computer Components Contemporary computer designs are based on concepts developed by John von Neumann at the Institute for Advanced Studies(IAS), Princeton in 1945 Referred to as the von Neumann architecture and is based on three key concepts: – Data and instructions are stored in a single read-write memory – The contents of this memory are addressable by location, without regard to the type of data contained there – Execution occurs in a sequential fashion (unless explicitly modified) from one instruction to the next – Hardwired program – The result of the process of connecting the various components in the desired configuration © 2016 Pearson Education, Inc., Ho boken, NJ. All rights reserved. The Von Neumann Architecture  Faculty of Computing and Informatics Group Discussion (pair up in groups of 2 and carry out this task ) Based on the Video Clip you just watched, take 2 minutes to answer the following questions:- 1. List the five components of the Von-Neumann architecture. 2. From the user input to the computer, how is data handled? 3. What is the function of the ALU? 4. What is the relationship between the Control unit and other computer components. 5. Data transfer between the processor and memory is Software A sequence of codes or instructions Part of the hardware interprets each Software instruction and generates control signals Provide a new sequence of codes for each new program instead of rewiring the hardware Major components: I/O CPU Component Instruction interpreter s Module of general-purpose arithmetic and logic functions I/O Components Input module Contains basic components for accepting data and instructions and converting them into an internal form of signals usable by the system Output module Means of reporting results © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  Action Categories Data Data transferred transferred to from or from a processor to peripheral memory or device by from memory Process transferring to processor between the or- Process processor and memor or-I/O an I/O module y Data Control process ing An instruction The processor may specify may perform that the some sequence of arithmetic or execution be logic altered operation on © 2016 Pearson Education, Inc., data Hoboken, NJ. All rights reserved. + I/O Function I/O module can exchange data directly with the processor Processor can read data from or write data to an I/O module In some cases it is desirable to allow I/O exchanges to occur directly with memory © 2016 Pearson Education, Inc., Ho boken, NJ. All rights reserved. The interconnection structure must support the following types of transfers: Memor Process I/O to I/O to Process y to or to or from process or to process memor memor or I/O An I/O or y y module is allowed to Processo exchange Processo r reads data r reads an Processo Processo directly data instructi r writes a r sends with from an on or a unit of data to memory I/O unit of data to the I/O without device data memory device going via an I/O from through module memory the processo r using direct memory access © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. + Computer Interconnection BUS Interconnection (shared) – Traditional bus architecture – High Performance bus architecture) Quick point Interconnection( Pairwise) © 2016 Pearson Education, Inc., Ho boken, NJ. All rights reserved. +  A communication Signals transmitted by any one device are available pathway connecting for reception by all other two or more devices devices attached to the Key characteristic is that bus it is a shared If two devices transmit during the same time period their signals will transmission medium overlap and become garbled Bus Typically consists of multiple communication lines Computer systems contain a number of different buses that provide Inte Each line is capable of transmitting signals representing binary 1 pathways between components at various levels of the computer rco system hierarchy and binary 0 nne The most common ctio System bus computer A bus that connects major computer interconnection structures are based n components on the use of one or (processor, memory, more system buses I/O) © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  Data Bus Data lines that provide a path for moving data among system modules May consist of 32, 64, 128, or more separate lines The number of lines is referred to as the width of the data bus The number of lines determines how many bits can be transferred at a time The width of the data bus is a key factor in determining overall system performance © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  Address Bus Control Bus Used to designate the source Used to control the access and the or destination of the data on use of the data and address lines the data bus – If the processor wishes to read a Because the data and address lines word of data from memory it puts the address of the desired are shared by all components there word on the address lines must be a means of controlling their use Width determines the Control signals transmit both maximum possible memory capacity of the system command and timing information among system modules Also used to address I/O ports Timing signals indicate the validity of – The higher order bits are used to data and address information select a particular module on the bus and the lower order bits select a memory location or I/O Command signals specify operations port within the module to be performed © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. Bus Interconnection Scheme © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. + Traditional Bus Architecture © 2016 Pearson Education, Inc., Ho boken, NJ. All rights reserved. + High Performance Bus Architecture © 2016 Pearson Education, Inc., Ho boken, NJ. All rights reserved. + Synchronous bus + Synchronous bus.. + Asynchronous bus + Peripheral Component Interconnect (PCI) A popular high bandwidth, processor independent bus that can function as a mezzanine or peripheral bus Delivers better system performance for high speed I/O subsystems PCI Special Interest Group (SIG) – Created to develop further and maintain the compatibility of the PCI specifications – PCI Express (PCIe) – Point-to-point interconnect scheme intended to replace bus-based schemes such as PCI – Key requirement is high capacity to support the needs of higher data rate I/O devices, such as Gigabit Ethernet – Another requirement deals with the need to support time dependent data streams © 2016 Pearson Education, Inc., Ho boken, NJ. All rights reserved. + Point to Point Interconnect  Quick Path Interconnect (QPI) The Intel QPI is a point-to point processor interconnect developed by Intel which replaced the front-side bus (FSB) in Xeon, Itanium, and certain desktop platforms starting in 2008. PCIe is a point-to-point interconnect intended to replace both PCI (a general-purpose system bus) and AGP (a bus used for graphics cards). It is based on the concept of lanes, which work by analogy to lanes on a highway. A single physical slot that you plug a card into + Point-to-Point Interconnect Principal reason for At higher and higher change was the data rates it becomes electrical constraints increasingly difficult to encountered with perform the increasing the synchronization and frequency of wide arbitration functions in synchronous buses a timely fashion A conventional shared bus on the same chip magnified the Has lower latency, difficulties of increasing higher data rate, and bus data rate and better scalability reducing bus latency to keep up with the processors © 2016 Pearson Education, Inc., Ho boken, NJ. All rights reserved. © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. Summary  Bus Interconnection structures Van Neuman  Bus Architectures  General purpose Vs  Synchronous Vs Asynchronous Bus Hardwired  Peripheral System Interconnect  Shared bus  Point to Point  PCIe  QPI  Complete Lab1 © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.