LEC16-4471029-MIPS uarch (multicycle) enhanced PDF

Intro to Microarchitecture : Multi-Cycle and Microprogrammed uArch 471029: Introduction to Computer Architecture 16th Lecture Disclaimer: Slides are mainly based on COD 5th textbook and also developed in part by Profs. Dohyung Kim @ KNU and Computer architecture course @ KAIST and SKKU...

Intro to Microarchitecture : Multi-Cycle and Microprogrammed uArch 471029: Introduction to Computer Architecture 16th Lecture Disclaimer: Slides are mainly based on COD 5th textbook and also developed in part by Profs. Dohyung Kim @ KNU and Computer architecture course @ KAIST and SKKU 1 Multi-Cycle Microarchitecture ¢ Goal: Let each instruction take (close to) only as much time it really needs ¢ Idea § Determine clock cycle time independently of instruction processing time § Each instruction takes as many clock cycles as it needs to take § Multiple state transitions per instruction § The states followed by each instruction is different 2 Remember: The “Process instruction” Step ¢ ISA specifies abstractly what AS’ should be, given an instruction and AS § It defines an abstract finite state machine where § State = programmer-visible state § Next-stage logic = instruction execution specification § From ISA point of view, there are no “intermediate states” between AS and AS’ during instruction execution § One state transition per instruction ¢ Microarchitecture implements how AS is transformed to AS’ § There are many choices in implementation § We can have programmer-invisible state to optimize the speed of instruction execution: multiple state transitions per instruction § Choice 1: AS à AS’ (transform AS to AS’ in a single clock cycle) § Choise 2: AS à AS+MS1 à AS+MS2 à AS+MS3 à AS’ (take multiple clock cycles to transform AS to AS’) 3 Multi-Cycle Microarchitecture AS = Architectural (programmer visible) state at the beginning of an instruction Step 1: Process part of instruction in one clock cycle Step 2: Process part of instruction in the next clock cycle … AS’ = Architectural (programmer visible) state at the end of a clock cycle 4 Benefits of Multi-Cycle Design ¢ Critical path design § Can keep reducing the critical path independently of the worst-case processing time of any instruction ¢ Bread and butter (common case) design § Spend time and resources on where it matters most §i.e., improve what the machine is really designed to do § Common case vs. uncommon case § e.g., ADD vs DIV (for example J) ¢ Balanced design § No need to provide more capability or resources than really needed § An instruction that needs resource X multiple times does not require multiple X’s to be implemented § Leads to more efficient hardware: Can reuse hardware components needed multiple times for an instruction § e.g., multiple ALUs in the single cycle machine 5 Downsides of Multi-Cycle Design ¢ Need to store the intermediate results at the end of each clock cycle § Hardware overhead for registers § Register setup/hold overhead paid multiple times for an instruction 6 Multi-Cycle Microarchitectures ¢ Key Idea for Realization § One can implement the “process instruction” stage as a finite state machine that sequences between states and eventually returns back to the “fetch instruction” state § A state is defined by the control signals asserted in it § Control signals for the next state determined in current state 7 A Basic Multi-Cycle Microarchitecture ¢ Instruction processing cycle divided into “states” § A stage in the instruction processing cycle can take multiple states ¢ A multi-cycle microarchitecture sequences from state to state to process an instruction § The behavior of the machine in a state is completely determined by control signals in that state ¢ The behavior of the entire processor is specified fully by a finite state machine ¢ In a state (clock cycle), control signals control two things: § How the datapath should process the data § How to generate the control signals for the next clock cycle 8 One Example Multi-Cycle uArchi. 9 Remember: Single-Cycle MIPS Processor Jump MemtoReg Control MemWrite Unit Branch ALUControl2:0 PCSrc 31:26 Op ALUSrc 5:0 Funct RegDst RegWrite CLK CLK CLK 0 25:21 WE3 SrcA Zero WE 0 PC' PC Instr A1 RD1 0 Result 1 A RD ALU 1 ALUResult ReadData A RD 1 Instruction 20:16 A2 RD2 0 SrcB Data Memory A3 1 Memory Register WriteData WD3 WD File 20:16 0 PCJump 15:11 1 WriteReg4:0 PCPlus4 + SignImm 4 15:0