Computer Organization and Architecture Chapter 8 - Input/Output PDF

Computer Organization and Architecture Designing for Performance 11th Edition, Global Edition Chapter 8 Input/Output Copyright © 2022 Pearson Education, Ltd. All Rights Reserv...

Computer Organization and Architecture Designing for Performance 11th Edition, Global Edition Chapter 8 Input/Output Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 8.1 Generic Model of an I/O Module Address Lines System Data Lines Bus Control Lines I/O Module Links to peripheral devices Copyright © 2022 Pearson Education, Ltd. All Rights Reserved External Devices Provide a means of Three exchanging data between the external environment categories: and the computer Human readable – Suitable for communicating with Attach to the computer by a the computer user link to an I/O module – Video display terminals (VDTs), printers – The link is used to exchange control, status, and data Machine readable between the I/O module and – Suitable for communicating with the external device equipment – Magnetic disk and tape systems, Peripheral device sensors and actuators – An external device connected Communication to an I/O module – Suitable for communicating with remote devices such as a terminal, a machine readable device, or another computer Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 8.2 Block Diagram of an External Device Control Status Data bits signals from signals to to and from I/O module I/O module I/O module Control Buffer Logic Transducer Data (device-unique) to and from environment Copyright © 2022 Pearson Education, Ltd. All Rights Reserved  Most common means of computer/user interaction Keyboard/Monitor User provides input through the keyboard The monitor displays data provided International Reference Alphabet by the computer (IRA) Basic unit of exchange is the character Keyboard Codes – Associated with each character is a code – Each character in this code is represented by a unique 7-bit binary code When the user depresses a key it generates ▪ 128 different characters can be an electronic signal that is interpreted by the represented transducer in the keyboard and translated into the bit pattern of the corresponding IRA code Characters are of two types: – Printable This bit pattern is transmitted to the I/O ▪ Alphabetic, numeric, and special module in the computer characters that can be printed on paper or displayed on a screen On output, IRA code characters are – Control transmitted to an external device from the I/O ▪ Have to do with controlling the printing module or displaying of characters ▪ Example is carriage return The transducer interprets the code and sends ▪ Other control characters are concerned the required electronic signals to the output with communications procedures device either to display the indicated character or perform the requested control function Copyright © 2022 Pearson Education, Ltd. All Rights Reserved I/O Functions The major functions for an I/O module fall into the following categories: Control and timing Coordinates the flow of traffic between internal resources and external devices Processor communication Involves command decoding, data, status reporting, address recognition Device communication Involves commands, status information, and data Data buffering Performs the needed buffering operation to balance device and memory speeds Error detection Detects and reports transmission errors Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 8.3 Block Diagram of an I/O Module Interface to Interface to System Bus External Device Data Data Registers External Device Data Status Interface Lines Logic Status/Control Registers Control Address Lines Data External I/O Device Logic Status Interface Control Logic Lines Control Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 8.3 Block Diagram of an I/O Module Programmed I/O Three techniques are possible for I/O operations: Programmed I/O – Data are exchanged between the processor and the I/O module – Processor executes a program that gives it direct control of the I/O operation – When the processor issues a command it must wait until the I/O operation is complete – If the processor is faster than the I/O module this is wasteful of processor time Interrupt-driven I/O – Processor issues an I/O command, continues to execute other instructions, and is interrupted by the I/O module when the latter has completed its work Direct memory access (DMA) – The I/O module and main memory exchange data directly without processor involvement Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Table 8.1 I/O Techniques No Interrupts Use of Interrupts I/O-to-memory transfer through Programmed I/O Interrupt-driven I/O processor Direct I/O-to-memory transfer Direct memory access (DMA) Copyright © 2022 Pearson Education, Ltd. All Rights Reserved I/O Commands There are four types of I/O commands that an I/O module may receive when it is addressed by a processor: 1) Control – used to activate a peripheral and tell it what to do 2) Test – used to test various status conditions associated with an I/O module and its peripherals 3) Read – causes the I/O module to obtain an item of data from the peripheral and place it in an internal buffer 4) Write – causes the I/O module to take an item of data from the data bus and subsequently transmit that data item to the peripheral Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 8.4 Three Techniques for Input of a Block of Data Issue Read Issue Read CPU I/O Issue Read CPU DMA command to CPU I/O command to Do something block command Do something I/O module I/O module else to I/O module else Read status Read status Interrupt Read status Interrupt of I/O I/O CPU of I/O of DMA I/O CPU module module module DMA CPU Not ready Next instruction Check Error Check Error status condition status condition (c) Direct memory access Ready Ready Read word Read word from I/O I/O CPU from I/O I/O CPU Module Module Write word Write word CPU memory CPU memory into memory into memory No No Done? Done? Yes Yes Next instruction Next instruction (a) Programmed I/O (b) Interrupt-driven I/O Figure 8.4 Three Techniques for © Copyright Input 2022of Pearson a Block of Data Education, Ltd. All Rights Reserved I/O Instructions With programmed I/O there is a close correspondence between the I/O-related instructions that the processor fetches from memory and the I/O commands that the processor issues to an I/O module to execute the instructions Each I/O device connected through I/O modules is given a unique identifier or address The form of the When the processor issues an I/O Memory-mapped I/O instruction depends command, the on the way in which command contains the external devices are address of the desired addressed device Thus each I/O module There is a single address space for A single read line and a single write must interpret the memory locations and I/O devices line are needed on the bus address lines to determine if the command is for itself Copyright © 2022 Pearson Education, Ltd. All Rights Reserved I/O Mapping Summary Memory mapped I/O – Devices and memory share an address space – I/O looks just like memory read/write – No special commands for I/O ▪ Large selection of memory access commands available Isolated I/O – Separate address spaces – Need I/O or memory select lines – Special commands for I/O ▪ Limited set Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 8.5 Memory-Mapped and Isolated I/O 7 6 5 4 3 2 1 0 516 Keyboard input data register 7 6 5 4 3 2 1 0 Keyboard input status 517 and control register 1 = ready Set to 1 to 0 = busy start read ADDRESS INSTRUCTION OPERAND COMMENT 200 Load AC "1" Load accumulator Store AC 517 Initiate keyboard read 202 Load AC 517 Get status byte Branch if Sign = 0 202 Loop until ready Load AC 516 Load data byte (a) Memory-mapped I/O ADDRESS INSTRUCTION OPERAND COMMENT 200 Load I/O 5 Initiate keyboard read 201 Test I/O 5 Check for completion Branch Not Ready 201 Loop until complete In 5 Load data byte (b) Isolated I/O Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 8.5 Memory-Mapped and Isolated I/O Interrupt-Driven I/O The problem with programmed I/O is that the processor has to wait a long time for the I/O module to be ready for either reception or transmission of data An alternative is for the processor to issue an I/O command to a module and then go on to do some other useful work The I/O module will then interrupt the processor to request service when it is ready to exchange data with the processor The processor executes the data transfer and resumes its former processing Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 8.6 Simple Interrupt Processing Hardware Software Device controller or other system hardware issues an interrupt Save remainder of process state information Processor finishes execution of current instruction Process interrupt Processor signals acknowledgment of interrupt Restore process state information Processor pushes PSW and PC onto control stack Restore old PSW and PC Processor loads new PC value based on interrupt Figure 8.6 Copyright © 2022 Pearson Simple Interrupt Education, Ltd. All Rights Reserved Processing Figure 8.7 Changes in Memory and Registers for an Interrupt T–M T–M Y N+1 Control Control Stack Stack T T N+1 Y+L Program Program Counter Counter Y Start Y Start Interrupt General Interrupt General Service Registers Service Registers Y + L Return Routine T Y + L Return Routine T–M Stack Stack Pointer Pointer Processor Processor T–M T N User's N User's N+1 N+1 Program Program Main Main Memory Memory (a) Interrupt occurs after instruction (b) Return from interrupt at location N Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 8.7 Changes in Memory and Registers for an Interrupt Design Issues Because there will be multiple I/O modules how does the processor determine which Two design device issued the interrupt? issues arise in implementing If multiple interrupt I/O: interrupts have occurred how does the processor decide which one to process? Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Device Identification Four general categories of techniques are in common use: Multiple interrupt lines – Between the processor and the I/O modules – Most straightforward approach to the problem – Consequently even if multiple lines are used, it is likely that each line will have multiple I/O modules attached to it Software poll – When the processor detects an interrupt it branches to an interrupt-service routine whose job is to poll each I/O module to determine which module caused the interrupt – Time consuming Daisy chain (hardware poll, vectored) – The interrupt acknowledge line is daisy chained through the modules – Vector – address of the I/O module or some other unique identifier – Vectored interrupt – processor uses the vector as a pointer to the appropriate device- service routine, avoiding the need to execute a general interrupt-service routine first Bus arbitration (vectored) – An I/O module must first gain control of the bus before it can raise the interrupt request line – When the processor detects the interrupt it responds on the interrupt acknowledge line – Then the requesting module places its vector on the data lines Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 8.8 Use of the 82C59A Interrupt Controller Slave 82C59A interrupt controller External device 00 IR0 External device 01 IR1 INT IR2 IR3 IR4 IR5 IR6 External device 07 IR7 Slave Master 82C59A 82C59A interrupt interrupt 80386 controller controller processor External device 08 IR0 IR0 External device 09 IR1 INT IR1 INT INTR IR2 IR2 IR3 IR3 IR4 IR4 IR5 IR5 IR6 IR6 External device 15 IR7 IR7 Slave 82C59A interrupt controller External device 56 IR0 External device 57 IR1 INT IR2 IR3 IR4 IR5 IR6 External device 63 IR7 Figure 8.8 Copyright © 2022 Use of the 82C59A Pearson Interrupt Education, Ltd. All Rights Reserved Controller Figure 8.9 The Intel 8255A Programmable Peripheral Interface PA3 1 40 PA4 Power +5 V PA2 2 39 PA5 supplies Group Group A GND Port A PA1 3 38 PA6 A I/O control (8) PA7 - PA0 PA0 4 37 PA7 RD 5 36 WR CS 6 35 Reset Bi-directional Group A GND 7 34 D0 data bus Data Port C I/O A1 8 33 D1 bus upper (4) PC7 - PC4 A0 9 8255A 32 D2 D7 - D0 buffer PC7 10 31 D3 8-bit Group B PC6 11 30 D4 internal Port C I/O PC5 12 29 D5 data bus Lower(4) PC3 - PC0 PC4 13 28 D6 RD PC3 14 27 D7 Read/ WR PC2 15 26 V write Group A1 Group B control B PC1 16 25 PB7 A0 Port B I/O logic control PC0 17 24 PB6 (8) PB7 - PB0 Reset PB0 18 23 PB5 CS PB1 19 22 PB4 PB2 20 21 PB3 (a) Block diagram (b) Pin layout Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 8.10 The Intel 8255A Control Word Group A Group B Don’t care D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D3 D2 D1 Port C (lower) 0 0 0 bit 0 of Port C 1 = Input 0 0 1 bit 1 of Port C 0 = Output 0 1 0 bit 2 of Port C Port B 0 1 1 bit 3 of Port C 1= Input 1 0 0 bit 4 of Port C 0 = Output 1 0 1 bit 5 of Port C Mode selection 1 1 0 bit 6 of Port C 0 = Mode 0 1 1 1 bit 7 of Port C 1 = Mode 1 Port C (upper) 1 = Input Bit set/reset Bit set/reset 0 = Output flag 1 = set Port A 0 = Active 0 = reset 1= Input 0 = Output Mode selection Mode set 00 = Mode 0 flag 01 = Mode 1 1 = Active 1X = Mode 2 (a) Mode definition of the 8255 control (b) Bit definitions of the 8255 control register to configure the 8255 register to modify single bits of port C Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 8.11 Keyboard/Display Interface to 8255A Interrupt request C3 A0 R0 A1 R1 A2 R2 A3 R3 INPUT A4 R4 KEYBOARD PORT A5 R5 A6 Shift A7 Control C4 Data ready C5 Acknowledge 82C55A B0 S0 B1 S1 B2 S2 B3 S3 OUTPUT DISPLAY B4 S4 PORT B5 S5 B6 Backspace B7 Clear C1 Data ready C2 Acknowledge C6 Blanking C0 C7 Clear line Interrupt request Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Drawbacks of Programmed and Interrupt- Driven I/O Both forms of I/O suffer from two inherent drawbacks: 1) The I/O transfer rate is limited by the speed with which the processor can test and service a device 2) The processor is tied up in managing an I/O transfer; a number of instructions must be executed for each I/O transfer When large volumes of data are to be moved a more efficient technique is direct memory access (DMA) Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 8.12 Typical DMA Block Diagram Data count Data lines Data register Address Address lines register Request to DMA Acknowledge from DMA Control Interrupt logic Read Write Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 8.13 DMA and Interrupt Breakpoints during an Instruction Cycle Time Instruction Cycle Processor Processor Processor Processor Processor Processor Cycle Cycle Cycle Cycle Cycle Cycle Fetch Decode Fetch Execute Store Process Instruction Instruction Operand Instruction Result Interrupt DMA Interrupt Breakpoints Breakpoint Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 8.14 Alternative DMA Configurations Processor DMA I/O I/O Memory (a) Single-bus, detached DMA Processor DMA DMA Memory I/O I/O I/O (b) Single-bus, Integrated DMA-I/O System bus Processor DMA Memory I/O bus I/O I/O I/O (c) I/O bus Figure 8.14 Copyright Alternative©DMA 2022Configurations Pearson Education, Ltd. All Rights Reserved Figure 8.15 8237 DMA Usage of System Bus CPU Data bus DREQ HRQ 8237 DMA Main Disk chip memory controller HLDA DACK Address bus Control bus (IOR, IOW, MEMR, MEMW) DACK = DMA acknowledge DREQ = DMA request HLDA = HOLD acknowledge HRQ = HOLD request Figure 8.15Copyright 8237 DMA Usage of System Bus © 2022 Pearson Education, Ltd. All Rights Reserved Fly-By DMA Controller Data does not pass 8237 contains four through and is not DMA channels stored in DMA chip Can be DMA can only programmed transfer data Can do memory to independently between an I/O port memory via register Any one of the and a memory channels may be address active at any Not between two moment I/O ports or two These channels are memory locations numbered 0, 1, 2, and 3 Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Direct Cache Access (DCA) DMA is not able to scale to meet the increased demand due to dramatic increases in data rates for network I/O Demand is coming primarily from the widespread deployment of 10-Gbps and 100-Gbps Ethernet switches to handle massive amounts of data transfer to and from database servers and other high-performance systems Another source of traffic comes from Wi-Fi in the gigabit range Network Wi-Fi devices that handle 3.2 Gbps and 6.76 Gbps are becoming widely available and producing demand on enterprise systems Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 8.16 Xeon E5-2600/4600 Chip Architecture Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Cache-Related Performance Issues (1 of 2) Network traffic is transmitted in the form of a sequence of protocol blocks called packets or protocol data units The lowest, or link, level protocol is typically Ethernet, so that each arriving and departing block of data consists of an Ethernet packet containing as payload the higher-level protocol packet The higher-level protocols are usually the Internet Protocol (IP), operating on top of Ethernet and the Transmission Control Protocol (TCP), operating on top of IP The Ethernet payload consists of a block of data with a TCP header and an IP header For outgoing data, Ethernet packets are formed in a peripheral component, such as in I/O controller or network interface controller (NIC) For incoming traffic, the I/O controller strips off the Ethernet information and delivers the TCP/IP packet to the host CPU Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Cache-Related Performance Issues (2 of 2) In a DMA scheme, when an application wishes to transmit data, it places that data in an application-assigned buffer in main memory The core transfers this to a system For both outgoing buffer in main memory and creates the necessary TCP and IP headers, which and incoming are also buffered in system memory The packet is then picked up via DMA traffic the core, for transfer via the NIC This activity engages not only main main memory, memory but also the cache Similar transfers between system and and cache are all application buffers are required for incoming traffic involved Copyright © 2022 Pearson Education, Ltd. All Rights Reserved  Packet Traffic Steps: Incoming Outgoing Packet arrives Packet transfer requested DMA Packet created NIC interrupts host Output operation invoked Retrieve descriptors and headers DMA transfer Cache miss occurs NIC signals completion Header is processed Driver frees buffer Payload transferred © 2018 Pearson Education, Inc., Hoboken, NJ. All rights reserved. Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Direct Cache Access Strategies Simplest strategy was implemented as a prototype on a number of Intel Xeon processors between 2006 and 2010 The DCA function in the memory This form of DCA applies only to controller sends a prefetch hint to the This enables the core to prefetch the incoming network traffic core as soon as the data is available in data packet from the system buffer system memory Much more substantial gains can be realized by avoiding the system buffer in main memory altogether For incoming packets, The packet and packet the core reads the data Implemented in Intel’s descriptor information It has no need to from the buffer and Xeon processor line, are accessed only access that data in the Cache injection transfers the packet referred to as Direct once in the system system buffer again payload to an Data I/O buffer by the core application buffer Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 8.17 Comparison of DMA and DDIO Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Evolution of the I/O Function 1. The CPU directly controls a 4. The I/O module is given direct peripheral device. access to memory via DMA. It can now move a block of data to or 2. A controller or I/O module from memory without involving the is added. The CPU uses CPU, except at the beginning and programmed I/O without end of the transfer. interrupts. 5. The I/O module is enhanced to 3. Same configuration as in become a processor in its own step 2 is used, but now right, with a specialized instruction interrupts are employed. set tailored for I/O The CPU need not spend time waiting for an I/O 6. The I/O module has a local operation to be performed, memory of its own and is, in fact, a thus increasing efficiency. computer in its own right. With this architecture a large set of I/O devices can be controlled with minimal CPU involvement. Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 8.18 I/O Channel Architecture Data and address channel to main memory Selector channel Control signal I/O I/O path to CPU Controller Controller (a) Selector Data and address channel to main memory Multi- plexor channel Control signal path to CPU I/O Controller I/O Controller I/O Controller I/O Controller (b) Multiplexor Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 8.18 I/O Channel Architecture Summary Input/Output Chapter 8 Direct Cache Access External devices I/O channels and I/O modules processors Programmed I/O External interconnection Interrupt-driven I/O standards Direct memory IBM zEnterprise EC12 access I/O structure Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Computer Organization and Architecture Designing for Performance 11th Edition, Global Edition Chapter 10 Number Systems Copyright © 2022 Pearson Education, Ltd. All Rights Reserved The Decimal System System based on decimal digits (0, 1, 2, 3, 4, 5, 6, 7, 8, 9) to represent numbers For example the number 83 means eight tens plus three: 83 = (8 * 10) + 3 The number 4728 means four thousands, seven hundreds, two tens, plus eight: 4728 = (4 * 1000) + (7 * 100) + (2 * 10) + 8 The decimal system is said to have a base, or radix, of 10. This means that each digit in the number is multiplied by 10 raised to a power corresponding to that digit’s position: 83 = (8 * 101) + (3 * 100) 4728 = (4 * 103) + (7 * 102) + (2 * 101) + (8 * 100) Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Decimal Fractions The same principle holds for decimal fractions, but negative powers of 10 are used. Thus, the decimal fraction 0.256 stands for 2 tenths plus 5 hundredths plus 6 thousandths: 0.256 = (2 * 10-1) + (5 * 10-2) + (6 * 10-3) A number with both an integer and fractional part has digits raised to both positive and negative powers of 10: 442.256 = (4 * 102) + (4 + 101) + (2 * 100) + (2 * 10-1) + (5 * 10-2) + (6 * 10-3) Most significant digit – The leftmost digit (carries the highest value) Least significant digit – The rightmost digit Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Table 10.1 Positional Interpretation of a Decimal Number 4 7 2 2 5 6 100s 10s 1s tenths hundredths thousandths 102 101 100 10-1 10-2 10-3 position 2 position 1 position 0 position –1 position –2 position –3 Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Positional Number Systems Each number is represented by a string of digits in which each digit position i has an associated weight ri, where r is the radix, or base, of the number system. The general form of a number in such a system with radix r is (... a3a2a1a0.a-1a-2a-3... )r where the value of any digit ai is an integer in the range 0 < ai < r. The dot between a0 and a-1 is called the radix point. Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Table 10.2 Positional Interpretation of a Number in Base 7 Position 4 3 2 1 0 –1 Value in Exponential Form 74 73 72 71 70 7–1 Decimal Value 2401 343 49 7 1 1/7 Copyright © 2022 Pearson Education, Ltd. All Rights Reserved The Binary System Only two digits, 1 and 0 Represented to the base 2 The digits 1 and 0 in binary notation have the same meaning as in decimal notation: 02 = 010 12 = 110 To represent larger numbers each digit in a binary number has a value depending on its position: 102 = (1 * 21) + (0 * 20) = 210 112 = (1 * 21) + (1 * 20) = 310 1002 = (1 * 22) + (0 * 21) + (0 * 20) = 410 and so on. Again, fractional values are represented with negative powers of the radix: 1001.101 = 23 + 20 + 2-1 + 2-3 = 9.62510 Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Converting Between Binary and Decimal Binary notation to decimal notation: – Multiply each binary digit by the appropriate power of 2 and add the results Decimal notation to binary notation: – Integer and fractional parts are handled separately Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Integers 1/2 For the integer part, recall that in binary notation, an integer represented by bm-1bm-2... b2b1b0 bi = 0 or 1 has the value (bm-1 * 2m-1) + (bm-2 * 2 m-2) +... + (b1 * 21) + b0 Suppose it is required to convert a decimal integer N into binary form. If we divide N by 2, in the decimal system, and obtain a quotient N1 and a remainder R0, we may write N = 2 * N1 + R0 R0 = 0 or 1 Next, we divide the quotient N1 by 2. Assume that the new quotient is N2 and the new remainder R1. Then N1 = 2 * N2 + R1 R1 = 0 or 1 so that N = 2(2N2 + R1) + R0 = (N2 * 22) + (R1 * 21) + R0 If next N2 = 2N3 + R2 we have N = (N3 * 23) + (R2 * 22) + (R1 * 21) + R0 Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Integers 2/2 Because N >N1 > N2... , continuing this sequence will eventually produce a quotient Nm-1 = 1 (except for the decimal integers 0 and 1, whose binary equivalents are 0 and 1, respectively) and a remainder Rm-2, which is 0 or 1. Then N = (1 * 2m-1) + (Rm-2 * 2m-2) +... + (R2 * 22) + (R1 * 21) + R0 which is the binary form of N. Hence, we convert from base 10 to base 2 by repeated divisions by 2. The remainders and the final quotient, 1, give us, in order of increasing significance, the binary digits of N. Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 10.1 Examples of Converting from Decimal Notation to Binary Notation for Integers Quotient Remainder 11 = 5 1 2 5 = 2 1 2 2 = 1 0 2 1 = 0 1 2 10112 = 1110 (a) 1110 Quotient Remainder 21 = 10 1 2 10 = 5 0 2 5 = 2 1 2 2 = 1 0 2 1 = 0 1 2 101012 = 2110 (b) 2110 Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 10.1 Examples of Converting from Decimal Notation to Binary Notation for Integers Fractions (1 of 2) For the fractional part, recall that in binary notation, a number with a value between 0 and 1 is represented by 0.b-1b-2b-3... bi = 0 or 1 and has the value (b-1 * 2-1) + (b-2 * 2-2) + (b-3 * 2-3)... This can be rewritten as 2-1 * (b-1 + 2-1 * (b-2 + 2-1 * (b-3 +... )... )) Suppose we want to convert the number F (0 < F < 1) from decimal to binary notation. We know that F can be expressed in the form F = 2-1 * (b-1 + 2-1 * (b-2 + 2-1 * (b-3 +... )... )) If we multiply F by 2, we obtain, 2 * F = b-1 + 2-1 * (b-2 + 2-1 * (b-3 +... )... ) Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Fractions (2 of 2) From this equation, we see that the integer part of (2 * F), which must be either 0 or 1 because 0 < F < 1, is simply b-1. So we can say (2 * F) = b-1 + F1, where 0 < F1 < 1 and where F1 = 2-1 * (b-2 + 2-1 * (b-3 + 2-1 * (b-4 +... )... )) To find b−2, we repeat the process. At each step, the fractional part of the number from the previous step is multiplied by 2. The digit to the left of the decimal point in the product will be 0 or 1 and contributes to the binary representation, starting with the most significant digit. The fractional part of the product is used as the multiplicand in the next step. Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 10.2 Examples of Converting from Decimal Notation to Binary Notation for Fractions Product Integer Part 0.110011 2 0.81 2 = 1.62 1 0.62 2 = 1.24 1 0.24 2 = 0.48 0 0.48 2 = 0.96 0 0.96 2 = 1.92 1 0.92 2 = 1.84 1 (a) 0.81 10 = 0.110011 2 (approximately) Product Integer Part 0.012 0.25 2 = 0.5 0 0.5 2 = 1.0 1 (b) 0.25 10 = 0.012 (exactly) Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Hexadecimal Notation 1/2 Binary digits are grouped into sets of four bits, called a nibble Each possible combination of four binary digits is given a symbol, as follows: 0000 = 0 0100 = 4 1000 = 8 1100 = C 0001 = 1 0101 = 5 1001 = 9 1101 = D 0010 = 2 0110 = 6 1010 = A 1110 = E 0011 = 3 0111 = 7 1011 = B 1111 = F Because 16 symbols are used, the notation is called hexadecimal and the 16 symbols are the hexadecimal digits Thus 2C16 = (216 * 161) + (C16 * 160) = (210 * 161) + (1210 * 160) = 44 Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Table 10.3 Decimal (base 10) 0 Binary (base 2) 0000 Hexadecimal (base 16) 0 Decimal, Binary, 1 2 0001 0010 1 2 and Hexadecimal 3 4 0011 0100 3 4 5 0101 5 6 0110 6 7 0111 7 8 1000 8 9 1001 9 10 1010 A 11 1011 B 12 1100 C 13 1101 D 14 1110 E 15 1111 F 16 0001 0000 10 17 0001 0001 11 18 0001 0010 12 31 0001 1111 1F 100 0110 0100 64 255 1111 1111 FF 256 0001 0000 0000 100 Copyright © 2022 Pearson Education, Ltd. All Rights Reserved  Hexadecimal Notation 2/2 Not only used for representing integers but also as a concise notation for representing any Reasons for using sequence of binary digits hexadecimal notation are: In most computers, binary data occupy some It is extremely easy to It is more compact than multiple of 4 bits, and convert between binary binary notation hence some multiple of a and hexadecimal notation single hexadecimal digit Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Summary Number Systems Chapter 10 Converting between The decimal system binary and decimal Positional number – Integers – Fractions systems The binary system Hexadecimal notation Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Computer Organization and Architecture Designing for Performance 11th Edition, Global Edition Chapter 11 Computer Arithmetic Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Arithmetic & Logic Unit (ALU) Part of the computer that actually performs arithmetic and logical operations on data All of the other elements of the computer system are there mainly to bring data into the ALU for it to process and then to take the results back out Based on the use of simple digital logic devices that can store binary digits and perform simple Boolean logic operations Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 11.1 ALU Inputs and Outputs Control Signals Flags ALU Operand Result Registers Registers Figure 11.1 ALU Inputs and Outputs Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Integer Representation In the binary number system arbitrary numbers can be represented with: – The digits zero and one – The minus sign (for negative numbers) – The period, or radix point (for numbers with a fractional component) For purposes of computer storage and processing we do not have the benefit of special symbols for the minus sign and radix point Only binary digits (0,1) may be used to represent numbers Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Sign-Magnitude Representation There are several alternative All of these alternatives involve treating the most significant (leftmost) bit in the word as a conventions used to represent sign bit negative as well as positive If the sign bit is 0 the number is positive integers If the sign bit is 1 the number is negative Sign-magnitude representation is the simplest form that employs a sign bit Addition and subtraction require a consideration of both the signs of the Drawbacks: numbers and their relative magnitudes to carry out the required operation There are two representations of 0 Because of these drawbacks, sign-magnitude representation is rarely used in implementing the integer portion of the ALU Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Table 11.1 Characteristics of Twos Complement Representation and Arithmetic Range -2n-1 through 2n-1 - 1 Number of Representations One of Zero Take the Boolean complement of each bit of the corresponding Negation positive number, then add 1 to the resulting bit pattern viewed as an unsigned integer. Add additional bit positions to the left and fill in with the value Expansion of Bit Length of the original sign bit. If two numbers with the same sign (both positive or both nega- Overflow Rule tive) are added, then overflow occurs if and only if the result has the opposite sign. To subtract B from A, take the twos complement of B and add Subtraction Rule it to A. Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Table 11.2 Alternative Representations for 4-Bit Integers Decimal Sign-Magnitude Twos Complement Biased Representation Representation Representation Representation +8 – – 1111 +7 0111 0111 1110 +6 0110 0110 1101 +5 0101 0101 1100 +4 0100 0100 1011 +3 0011 0011 1010 +2 0010 0010 1001 +1 0001 0001 1000 –0 0000 0000 0111 +0 1000 – – –1 1001 1111 0110 –2 1010 1110 0101 –3 1011 1101 0100 –4 1100 1100 0011 –5 1101 1011 0010 –6 1110 1010 0001 –7 1111 1001 0000 –8 – 1000 – Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 11.2 Use of a Value Box for Conversion between Twos Complement Binary and Decimal –128 64 32 16 8 4 2 1 (a) An eight-position two's complement value box –128 64 32 16 8 4 2 1 1 0 0 0 0 0 1 1 –128 +2 +1 = –125 (b) Convert binary 10000011 to decimal –128 64 32 16 8 4 2 1 1 0 0 0 1 0 0 0 –120 = –128 +8 (c) Convert decimal –120 to binary Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 11.2 Use of a Value Box for Conversion Range Extension Range of numbers that can be expressed is extended by increasing the bit length In sign-magnitude notation this is accomplished by moving the sign bit to the new leftmost position and fill in with zeros This procedure will not work for twos complement negative integers – Rule is to move the sign bit to the new leftmost position and fill in with copies of the sign bit – For positive numbers, fill in with zeros, and for negative numbers, fill in with ones – This is called sign extension Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Fixed-Point Representation Programmer can use the same representation for The radix point (binary binary fractions by scaling point) is fixed and assumed the numbers so that the to be to the right of the binary point is implicitly rightmost digit positioned at some other location Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Negation Twos complement operation – Take the Boolean complement of each bit of the integer (including the sign bit) – Treating the result as an unsigned binary integer, add 1 +18 = 00010010 (twos complement) bitwise complement = 11101101 + 1 11101110 = -18 The negative of the negative of that number is itself: -18 = 11101110 (twos complement) bitwise complement = 00010001 + 1 00010010 = +18 Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Negation Special Case 1 0 = 00000000 (twos complement) Bitwise complement = 11111111 Add 1 to LSB + 1 Result 100000000 Overflow is ignored, so: -0=0 Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Negation Special Case 2 -128 = 10000000 (twos complement) Bitwise complement = 01111111 Add 1 to LSB + 1 Result 10000000 So: -(-128) = -128 X Monitor MSB (sign bit) It should change during negation Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 11.3 Addition of Numbers in Twos Complement Representation 1001 = –7 1100 = –4 +0101 = 5 +0100 = 4 1110 = –2 10000 = 0 (a) (–7) + (+5) (b) (–4) + (+4) 0011 = 3 1100 = –4 +0100 = 4 +1111 = –1 0111 = 7 11011 = –5 (c) (+3) + (+4) (d) (–4) + (–1) 0101 = 5 1001 = –7 +0100 = 4 +1010 = –6 1001 = Overflow 10011 = Overflow (e) (+5) + (+4) (f) (–7) + (–6) Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Overflow Rule If two numbers are added, and they are both positive or both negative, then overflow occurs if and only if the result has the opposite sign. Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Subtraction Rule To subtract one number (subtrahend) from another (minuend), take the twos complement (negation) of the subtrahend and add it to the minuend. Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 11.4 Subtraction of Numbers in Twos Complement Representation (M − S) 0010 = 2 0101 = 5 +1001 = –7 +1110 = –2 1011 = –5 10011 = 3 (a) M = 2 = 0010 (b) M = 5 = 0101 S = 7 = 0111 S = 2 = 0010 –S = 1001 –S = 1110 1011 = –5 0101 = 5 +1110 = –2 +0010 = 2 11001 = –7 0111 = 7 (c) M =–5 = 1011 (d) M = 5 = 0101 S = 2 = 0010 S =–2 = 1110 –S = 1110 –S = 0010 0111 = 7 1010 = –6 +0111 = 7 +1100 = –4 1110 = Overflow 10110 = Overflow (e) M = 7 = 0111 (f) M = –6 = 1010 S = –7 = 1001 S = 4 = 0100 –S = 0111 –S = 1100 Copyright Figure 11.4 Subtraction of Numbers © Complement in Twos 2022 Pearson Education, Representation (M –Ltd. S) All Rights Reserved Figure 11.5 Geometric Depiction of Twos Complement Integers subtraction addition subtraction addition of positive of positive of positive of positive numbers 0000 numbers numbers 000…0 numbers 1111 0001 111…1 1110 0010 -1 0 1101 -1 0 +1 -2 +2 0011 -3 +3 1100 -4 +4 0100 110…0 –2n–2 n–2 2 010…0 -5 +5 1011 -6 +6 -7 -8 +7 0101 n–1 –2n–1 2 –1 1010 0110 1001 0111 011…1 1000 100…0 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 n–1 n–1 –2 2 –1 –2n–1–1 2 n–1 (a) 4-bit numbers (b) n-bit numbers Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 11.6 Block Diagram of Hardware for Addition and Subtraction B Register A Register Complementer SW OF Adder OF = overflow bit SW = Switch (select addition or subtraction) Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 11.7 Multiplication of Unsigned Binary Integers 1011 Multiplicand (11) 1101 Multiplier (13) 1011 0000 Partial products 1011 1011 10001111 Product (143) Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 11.8 Hardware Implementation of Unsigned Binary Multiplication Multiplicand Mn-1 M0 Add Shift and Add n-Bit Adder Control Logic Shift Right C An-1 A0 Qn-1 Q0 Multiplier (a) Block Diagram C A Q M 0 0000 1101 1011 Initial Values 0 1011 1101 1011 Add First 0 0101 1110 1011 Shift Cycle Second 0 0010 1111 1011 Shift Cycle 0 1101 1111 1011 Add Third 0 0110 1111 1011 Shift Cycle 1 0001 1111 1011 Add Fourth 0 1000 1111 1011 Shift Cycle (b) Example from Figure 9.7 (product in A, Q) Copyright Figure 11.8 Hardware © 2022 Pearson Implementation of Education, Ltd. All Rights Reserved Unsigned Binary Multiplication Figure 11.9 Flowchart for Unsigned Binary Multiplication START C, A 0 M Multiplicand Q Multiplier Count n No Yes Q0 = 1? C, A A + M Shift right C, A, Q Count Count – 1 No Yes Count = 0? END Product in A, Q Copyright © 2022 Pearson Education, Ltd. All Rights Reserved  Figure 11.10 Multiplication of Two Unsigned 4-Bit Integers Yielding an 8-Bit Result 1011 ´1101 00001011 1011 ´ 1 ´ 20 00000000 1011 ´ 0 ´ 21 00101100 1011 ´ 1 ´ 22 01011000 1011 ´ 1 ´ 23 10001111 ure 11.10 Multiplication of Two Unsigned 4-Bit Integers Yielding an 8 Result Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 11.11 Comparison of Multiplication of Unsigned and Twos Complement Integers 1001 (9) 1001 (–7) ´0011 (3) ´0011 (3) 00001001 1001 ´ 20 11111001 (–7) ´ 20 = (–7) 00010010 1001 ´ 21 11110010 (–7) ´ 21 = (–14) 00011011 (27) 11101011 (–21) (a) Unsigned integers (b) Twos complement integers Figure 11.11 Comparison of Multiplication of Unsigned and Twos Complement Integers Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 11.12 Booth’s Algorithm for Twos Complement Multiplication START A 0, Q-1 0 M Multiplicand Q Multiplier Count n = 10 Q0 , Q-1 = 01 = 11 = 00 A A–M A A+M Arithmetic Shift Right: A, Q, Q -1 Count Count – 1 No Yes Count = 0? END Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 11.13 Example of Booth’s Algorithm (7 × 3) A Q Q-1 M 0000 0011 0 0111 Initial Values 1001 0011 0 0111 A A - M First 1100 1001 1 0111 Shift Cycle Second 1110 0100 1 0111 Shift Cycle 0101 0100 1 0111 A A + M Third 0010 1010 0 0111 Shift Cycle Fourth 0001 0101 0 0111 Shift Cycle Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 11.14 Examples Using Booth’s Algorithm 0111 0111 ´0011 (0) ´1101 (0) 11111001 1–0 11111001 1–0 0000000 1–1 0000111 0–1 000111 0–1 111001 1–0 00010101 (21) 11101011 (–21) (a) (7) ´ (3) = (21) (b) (7) ´ (–3) = (–21) 1001 1001 ´0011 (0) ´1101 (0) 00000111 1–0 00000111 1–0 0000000 1–1 1111001 0–1 111001 0–1 000111 1–0 11101011 (–21) 00010101 (21) (c) (–7) ´ (3) = (–21) (d) (–7) ´ (–3) = (21) Figure 11.14 Examples Using Copyright © 2022Booth's Algorithm Pearson Education, Ltd. All Rights Reserved  Figure 11.15 Example of Division of Unsigned Binary Integers 00001101 Quotient Divisor 1011 10010011 Dividend 1011 001110 1011 Partial 001111 remainders 1011 100 Remainder igure 11.15 Example of Division Copyright © of 2022Unsigned Pearson Education,Binary Ltd. All RightsIntegers Reserved Figure 11.16 Flowchart for Unsigned Binary Division START A 0 M Divisor Q Dividend Count n Shift Left A, Q A A–M No Yes A < 0? Q0 0 Q0 1 A A+M Count Count – 1 No Yes Count = 0? END Quotient in Q Remainder in A Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 11.17 Example of Restoring Twos Complement Division (7/3) A Q 0000 0111 Initial value 0000 1110 Shift 1101 Use twos complement of 0011 for subtraction 1101 Subtract 0000 1110 Restore, set Q0 = 0 0001 1100 Shift 1101 1110 Subtract 0001 1100 Restore, set Q0 = 0 0011 1000 Shift 1101 0000 1001 Subtract, set Q0 = 1 0001 0010 Shift 1101 1110 Subtract 0001 0010 Restore, set Q0 = 0 Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 11.17 Example of Restoring Twos Complement Division (7/3) Floating-Point Representation Principles With a fixed-point notation it is possible to represent a range of positive and negative integers centered on or near 0 By assuming a fixed binary or radix point, this format allows the representation of numbers with a fractional component as well Limitations: – Very large numbers cannot be represented nor can very small fractions – The fractional part of the quotient in a division of two large numbers could be lost Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 11.18 Typical 32-Bit Floating-Point Format sign of significand 8 bits 23 bits biased exponent significand (a) Format 1.1010001 210100 = 0 10010011 10100010000000000000000 = 1.6328125 220 -1.1010001 210100 = 1 10010011 10100010000000000000000 = –1.6328125 220 1.1010001 2-10100 = 0 01101011 10100010000000000000000 = 1.6328125 2–20 -1.1010001 2-10100 = 1 01101011 10100010000000000000000 = –1.6328125 2–20 (b) Examples Figure 11.18 Typical 32-Bit Floating-Point Format Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Floating-Point Significand The final portion of the word Any floating-point number can be expressed in many ways The following are equivalent, where the significand is expressed in binary form: 0.110 * 25 110 * 22 0.0110 * 26 Normal number – The most significant digit of the significand is nonzero Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 11.19 Expressible Numbers in Typical 32-Bit Formats Expressible Integers Number –231 0 231 – 1 Line (a) Twos Complement Integers Negative Positive Underflow Underflow Negative Expressible Negative Expressible Positive Positive Overflow Numbers Numbers Overflow Zero Number – (2 – 2–23) 2128 –2–127 0 2–127 (2 – 2–23) 2128 Line (b) Floating-Point Numbers Figure 11.19 Expressible Numbers in Typical 32-Bit Formats Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 11.20 Density of Floating-Point Numbers –n 0 n 2n 4n Figure 11.20 Density of Floating-Point Numbers Copyright © 2022 Pearson Education, Ltd. All Rights Reserved IEEE Standard 754 Standard was developed to facilitate the portability of programs from one Most important floating-point processor to another and to representation is defined encourage the development of sophisticated, numerically oriented programs Standard has been widely adopted and is used on IEEE 754-2008 covers both virtually all contemporary binary and decimal floating- processors and arithmetic point representations coprocessors Copyright © 2022 Pearson Education, Ltd. All Rights Reserved IEEE 754-2008 Defines the following different types of floating-point formats: Arithmetic format – All the mandatory operations defined by the standard are supported by the format. The format may be used to represent floating-point operands or results for the operations described in the standard. Basic format – This format covers five floating-point representations, three binary and two decimal, whose encodings are specified by the standard, and which can be used for arithmetic. At least one of the basic formats is implemented in any conforming implementation. Interchange format – A fully specified, fixed-length binary encoding that allows data interchange between different platforms and that can be used for storage. Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 11.21 IEEE 754 Formats sign biased bit exponent trailing significand field 8 bits 23 bits (a) binary32 format sign biased bit exponent trailing significand field 11 bits 52 bits (b) binary64 format sign bit biased trailing significand field exponent 15 bits 112 bits (c) binary128 format Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 11.21 IEEE 754 Formats Additional Formats Extended Precision Formats Provide additional bits in the exponent Extendable Precision Format (extended range) and in the significand (extended precision) Precision and range are defined under user control Lessens the chance of a final result that May be used for intermediate has been contaminated by excessive calculations but the standard roundoff error places no constraint or format or length Lessens the chance of an intermediate overflow aborting a computation whose final result would have been representable in a basic format Affords some of the benefits of a larger basic format without incurring the time penalty usually associated with higher precision Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Table 11.6 Floating-Point Numbers and Arithmetic Operations Floating-Point Numbers Arithmetic Operations X = XS  BXE Y = YS  BYE X + Y = (XS  BXE-YE + YS)  BYE X – Y = (XS  BXE-YE – YS)  BYE  XE  YE X  Y = (XSYS)  BXE+YE X Y = ( )B XS YS XE-YE Examples: X = 0.3  102 = 30 Y = 0.2  103 = 200 X + Y = (0.3  102-3 + 0.2)  103 = 0.23  103 = 230 X – Y = (0.3  102-3 – 0.2)  103 = ( – 0.17)  103 = –170 X  Y = (0.3  0.2)  102+3 = 0.06  105 = 6000 X  Y = (0.3  0.2)  102-3 = 1.5  10-1 = 0.15 Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 11.22 Floating-Point Addition and Subtraction (Z  X  Y) RETURN Round Yes result ADD SUBTRACT Yes Add Exponents signed equal? significands Change Results No normalized? sign of Y No Yes Increment No Z 0 Significand smaller No =0? exponent X = 0? Y = 0? Shift No significand Yes RETURN left Yes Shift No significand Significand Z Y Z X right overflow? Decrement exponent Yes RETURN Shift No significand No Exponent Significand right Yes =0? underflow? Yes Increment exponent Report Put other RETURN number in Z underflow Yes Report Exponent No RETURN overflow overflow? RETURN Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 11.22 Floating-Point Addition and Subtraction (Z X ± Y) Figure 11.23 Floating-Point Multiplication (Z  X  Y) MULTIPLY No No X = 0? Y = 0? Add Exponents Yes Yes Z 0 Subtract Bias RETURN Exponent Yes Report Overflow? Overflow No Exponent Yes Report Underflow? Underflow No Multiply Significands Normalize Round RETURN Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 11.24 Floating-Point Division (Z  X/Y) DIVIDE No No X = 0? Y = 0? Subtract Exponents Yes Yes Z 0 Z ∞ Add Bias RETURN Exponent Yes Report Overflow? Overflow No Exponent Yes Report Underflow? Underflow No Divide Significands Normalize Round RETURN Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Figure 11.25 The Use of Guard Bits x = 1.000.....00 ´ 21 x =.100000 ´ 161 –y = 0.111.....11 ´ 21 –y =.0FFFFF ´ 161 z = 0.000.....01 ´ 21 z =.000001 ´ 161 = 1.000.....00 ´ 2–22 =.100000 ´ 16–4 (a) Binary example, without guard bits (c) Hexadecimal example, without guard bits x = 1.000.....00 0000 ´ 21 x =.100000 00 ´ 161 –y = 0.111.....11 1000 ´ 21 –y =.0FFFFF F0 ´ 161 z = 0.000.....00 1000 ´ 21 z =.000000 10 ´ 161 = 1.000.....00 0000 ´ 2–23 =.100000 00 ´ 16–5 (b) Binary example, with guard bits (d) Hexadecimal example, with guard bits Figure 11.25 The Use of Guard Bits Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Precision Considerations Rounding IEEE standard approaches: – Round to nearest: ▪ The result is rounded to the nearest representable number. – Round toward +∞ : ▪ The result is rounded up toward plus infinity. – Round toward -∞: ▪ The result is rounded down toward negative infinity. – Round toward 0: ▪ The result is rounded toward zero. Copyright © 2022 Pearson Education, Ltd. All Rights Reserved Interval Arithmetic Provides an efficient method for monitoring and controlling errors in Minus infinity and rounding to plus floating-point computations by are useful in implementing interval producing two values for each arithmetic result The two values correspond to the lower and upper endpoints of an interval that contains the true result Truncation The width of the interval indicates the accuracy of the result Round toward zero Extra bits are ignored If the endpoints are not Simplest technique representable then the interval endpoints are rounded down and