Microprocessors Past Paper PDF

@DU Helpers 2021 Microprocessors (1) Question Bank Answers 1. The memory above the first 1M byte is called …………… A. TPA B. System area C. extended memory D. Cache memory 2. The First 1M byte of memory often called …………… A. Real memory B. Sy...

@DU Helpers 2021 Microprocessors (1) Question Bank Answers 1. The memory above the first 1M byte is called …………… A. TPA B. System area C. extended memory D. Cache memory 2. The First 1M byte of memory often called …………… A. Real memory B. System area C. Extended memory D. Cache memory 3. ……… is a high-speed temporary storage location for data moving between memory and the CPU A. Real memory B. System area C. Extended memory D. Cache memory 4. ………… is the first microprocessor that has 8 KB cache memory. A. Intel 80386 B. Intel 80486 C. Intel 80286 D. Intel Pentium 5. ……… is the first microprocessor that addressed 16M-byte memory system instead of a 1M-byte system. A. Intel 80386 B. Intel 80486 C. Intel 80286 D. Intel Pentium 6. ……………... requests a memory location from the memory or an I/O location from the I/O devices. A. Address bus B. Data bus C. control bus D. Memory 7. …………………. transfers information between the microprocessor and its memory and I/O address space A. Address bus B. Data bus C. control bus D. Memory 8. ……………. lines select and cause memory or I/O to perform a read or write operation. A. Address bus B. Data bus C. control bus D. Memory 9. What is the purpose of the IORC signal? A. Memory write control B. I/O read control C. I/O write control D. Memory read control  @DU Helpers 2021 10.What is the purpose of the IOWC signal? A. Memory write control B. I/O read control C. I/O write control D. Memory read control 11.What is the purpose of the MWTC signal? A. Memory write control B. I/O read control C. I/O write control D. Memory read control 12.What is the purpose of the MRDC signal? A. Memory write control B. I/O read control C. I/O write control D. Memory read control 13.A ……………... is the set of common connections that carry the same type of information. A. bus B. ALU C. EU D. BIU 14. ……………. map has two main areas; a TBA and system area A. Windows memory B. Extended memory C. Dos memory D. Dos and Windows memory 15.The memory size depends on the …………… A. address bus width B. data bus width C. control bus width D. system area width 16. In 80386EX microprocessor, if the data bus width is 16-bit and the address bus width is 26-bit, the memory size is ………. A. 64 KB B. 64 MB C. 64 GB D. 128 MB 17. In 8086 microprocessor, if the data bus width is 16-bit and the address bus width is 20-bit, the memory size is ………. A. 1 KB B. 1 MB C. 10 MB D. 10 KB 18.In 80286 microprocessor, the address bus width is 24-bit, the memory size is ………… A. 16 KB B. 16 GB C. 16 MB D. 16 Bytes  @DU Helpers 2021 19.In Pentium microprocessor, the address bus width is 32-bit, the memory size is ……… A. 4 KB B. 4 MB C. 4 GB D. 4 Bytes 20.In Pentium 4 microprocessor, the address bus width is 32- bit, the memory size is ……… A. 64 GB B. 64 MB C. 4 GB D. 64 KB 21.The size of TPA in Windows memory map is ……… A. 2 GB B. 640 KB C. 384 KB D. 4 MB 22.The size of system area in Windows memory map is ……… A. 2 GB B. 640 KB C. 384 KB D. 4 MB 23.The size of TPA in DOS memory map is ……… A. 2 GB B. 640 KB C. 384 KB D. 4 MB 24.The size of system area in DOS memory map is ……… A. 2 GB B. 640 KB C. 384 KB D. 4 MB 25.The function of the microprocessor is ……… A. Data transfer between itself and the memory B. Program flow via simple decisions C. Simple arithmetic and logic operations D. All the above 26. ……… fetches instructions, reads data from memory and I/O ports, writes data to memory and I/O ports A. BIU (Bus interface Unit) B. EU (Execution Unit) C. Programming Unit D. ALU (Arithmetic and Logic Unit) 27.…………… executes instructions that have already been fetched A. BIU (Bus interface Unit) B. EU (Execution Unit) C. Programming Unit D. Application Unit 28.Code segment register in microprocessor 8086 consists of ……………… A. 8-bit B. 32-bit C. 16-bit D. 64-bit  @DU Helpers 2021 29.Data segment register in microprocessor 8086 consists of ………… A. 8-bit B. 32-bit C. 16-bit D. 64-bit 30.Stack segment register in microprocessor 8086 consists of ……………… A. 8-bit B. 32-bit C. 16-bit D. 64-bit 31. The Intel 8086 microprocessor is a................ processor A. 8-bit B. 16-bit C. 32-bit D. 4-bit 32. In 8086 microprocessor, the address bus is.............. bit wide A. 32-bit B. 16-bit C. 20-bit D. 8-bit 33. In 8086 microprocessor, the 1 MB of memory can be divided into group of segments, the maximum size of each segment is …………… A. 64 Kbyte B. 32 Kbyte C. 1 Kbyte D. 16 Kbyte 34.……………… contains the base or start of the current code segment A. Code segment register (CS) B. Data segment register (DS) C. Stack segment register (SS) D. Extra segment register (ES) 35. ……………… register contains the 16-bit offset address pointing to the next instruction code within the 64KB of the code segment area A. Source index (SI) B. Instruction pointer (IP) C. Stack pointer (SP) D. Base pointer (BP) 36. ……………… points to the current data segment A. Code segment register (CS) B. Data segment register (DS) C. Stack segment register (SS) D. Extra segment register (ES) 37. …………… register contains the 16-bit offset address used with data segment area A. Source index (SI) B. Destination Index (DI) C. Stack pointer (SP) D. Source index (SI) or Destination Index (DI)  @DU Helpers 2021 38. ……………… points to the current stack A. Code segment register (CS) B. Data segment register (DS) C. Stack segment register (SS) D. Extra segment register (ES) 39.In the Stack, the memory location is addressed by…………… A. Stack pointer (SP) B. Instruction pointer (IP) C. Base pointer (BP) D. Stack pointer (SP) or Base pointer (BP) 40.The ability of a computer to overlap the execution of instructions is known as…………… A. Parallel processing B. Serial processing C. Pipelining D. Distributed processing 41.If the computer execute instructions one at a time, this is called……………… A. Parallel processing B. Serial processing C. Pipelining D. Distributed processing 42.The ability of a computer to execute two instructions at the same time is known as………………… A. Parallel processing B. Serial processing C. Pipelining D. Distributed processing 43. In microprocessor 8086, the AX consists of ……………… A. 8-bit B. 32-bit C. 16-bit D. 64-bit 44. In microprocessor 8086, the BL register consists of ……………… A. 8-bit B. 32-bit C. 16-bit D. 64-bit 45.The flag register of 8086 microprocessor is responsible for indicating ………… A. The result of addition B. The condition of memory C. The condition of result of ALU operations D. The result of subtraction 46. The ………….. bit is set when there is a carry in case of addition or a borrow in case of subtraction A. Overflow flag (OF) B. Zero flag (ZF) C. Sign flag (SF) D. Carry flag (CF) 47. The............. bit is set if the result of the computation or comparison performed by an instruction is zero A. Overflow flag (OF) B. Zero flag (ZF) C. Sign flag (SF) D. Carry flag (CF)  @DU Helpers 2021 48. The ….......... bit is set when the result of any computation is negative A. Overflow flag (OF) B. Zero flag (ZF) C. Sign flag (SF) D. Carry flag (CF) 49. In the real mode, if the segment register value is E001H, the starting address of the segment is ……… A. E001H B. E0001H C. E0010H D. E0101H 50. In the real mode, if the segment register value is 1234H, the ending address of the segment is ………… A. 11233H B. 2233FH C. 12340H D. 123410H 51. In the real mode, the value of the physical address of the B2C0 : FA12 combination is …………. A. 1ACD2H B. B2C0H C. FA12H D. C2612H 52. In the real mode, the value of the physical address of the 0100 : ABCD combination is …………. A. 01000H B. ACCDH C. BBCDH D. ABCDH 53. In the real mode, the unknown value of the A000 : ???? = A0123 physical address is …………. A. 123H B. 96123H C. 1230H D. 95123H 54. In the real mode, the unknown value of the ???? : 14DA = 235DA physical address is ………… A. 22100H B. 2210H C. 221000H D. 221H 55.The windows operates in…………… A. real mode B. protected mode C. conventional mode D. either real mode or conventional mode 56. The ….............. describes the memory segment’s location, length, and access rights A. selector B. descriptor C. application D. Microprocessor 57. The length of the descriptor for the 80286 and 80386 through Pentium II microprocessor is………… A. 16 bytes B. 16-bit C. 8- bit D. 8 bytes  @DU Helpers 2021 58.The maximum length of the local and global descriptor tables is ………… A. 64 bytes B. 64KB C. 64-bit D. 16KB 59.In the descriptor format of 80286 microprocessor, the base address consists of ………… A. 3 bytes B. 4 bytes C. 2 bytes D. 2.5 bytes 60.In the descriptor format of 80286 microprocessor, the limit consists of ………… A. 3 bytes B. 4 bytes C. 2 bytes D. 2.5 bytes 61. In the descriptor format of 80386 through Pentium II microprocessor, the base address consists of A. 3 bytes B. 4 bytes C. 2 bytes D. 2.5 bytes 62.In the descriptor format of 80386 through Pentium II microprocessor, the limit consists of ………… A. 3 bytes B. 4 bytes C. 2 bytes D. 2.5 bytes 63. In the 80286 microprocessor, if a segment begins at memory location F00000H and ends at location F000FFH, the limit is………… A. 00FFH B. 0FF0H C. FF00H D. F0F0H 64. In the 80386 through Pentium II microprocessor, if the descriptor has a base address = 23000000H and a limit = 012FFH, and G=0, the segment end is ………… A. 230012FFH B. 230102FFH C. 23000000H D. 012FFH 65. In the 80386 through Pentium II microprocessor, if the descriptor has a base address = 23000000H and a limit = 012FFH, and G=0, the segment size is ………… A. 012FFH B. 1300H C. 1301H D. 012FF0H 66. In the 80386 through Pentium II microprocessor, if the descriptor has a base address = 23000000H and a limit = 012FFH, and G=1, the segment end is ………… A. 230012FFH B. 23000000H C. 242FFFFFH D. 012FFFFFH  @DU Helpers 2021 67. In the 80386 through Pentium II microprocessor, if the descriptor has a base address = 23000000H and a limit = 012FFH, and G=1, the segment size is ………… A. 012FFH B. 1300000H C. 1300H D. 012FFFFFH 68. In 80286 microprocessor, if the segment register contains a selector of 0004H, the descriptor is chosen from ………… A. local Descriptor table B. global Descriptor table C. either local or global descriptor tables D. local and descriptor tables together 69. In 80286 microprocessor, if the Access Right byte in the descriptor contains 98H, the descriptor describes ………… A. stack segment B. code segment C. data segment D. extra segment 70.The instruction, MOV BX, CX is an example of A. register addressing mode B. direct addressing mode C. immediate addressing mode D. based indexed addressing mode 71.The instruction, MOV AX, 1234H is an example of A. register addressing mode B. direct addressing mode C. immediate addressing mode D. based indexed addressing mode 72.The instruction, MOV AX, [2500H] is an example of A. immediate addressing mode B. direct addressing mode C. indirect addressing mode D. register addressing mode 73.The instruction, MOV AX,[BX] is an example of A. direct addressing mode B. register addressing mode C. register relative addressing mode D. register indirect addressing mode 74.The instruction, MOV AX, [BX+1000H] is an example of A. direct addressing mode B. register addressing mode C. register relative addressing mode D. register indirect addressing mode 75.The instruction, MOV AX, [BX+DI] is an example of A. base plus index addressing mode B. register addressing mode C. base relative plus index addressing mode D. register indirect addressing mode  @DU Helpers 2021 76.The instruction, MOV AX, [BX+SI +100] is an example of A. base plus index addressing mode B. base relative plus index addressing mode C. register relative addressing mode D. register indirect addressing mode 77. Suppose that DS=0200H, BX=0300H, and DI=400H. Determine the memory address accessed by MOV AL, [1234H], assuming real mode operation A. 3534H B. 3934H C. 3234H D. 1434H 78. Suppose that DS=1000H, SS=2000H, BP=1000H, BX=2000, and DI= 0100H. Determine the memory address accessed by MOV AL, [BP+DI], assuming real mode operation A. 11100H B. 21100H C. 13100H D. 23100H 79. Suppose that DS=1000H, SS=2000H, BP=1000H, BX=200, and DI= 0100H. Determine the memory address accessed by MOV AL, [BX+DI], assuming real mode operation A. 11300H B. 21300H C. 20300H D. 10300H 80. Suppose that DS=1000H, SS=2000H, BP=1500H, BX=0100, and SI=0200H. Determine the address accessed by MOV AL, [BP+SI], assuming real mode operation A. 21700H B. 11700H C. 21800H D. 11800H 81. Suppose that DS=1000H, SS=2000H, BP=1500H, BX=0100, and SI=0200H. Determine the address accessed by MOV [SI+100H], EAX, assuming real mode operation A. 10300H B. 20300H C. 10400H D. 20400H 82. The memory location addressed by the CS=3456H and IP=ABCDH real mode register combinations is………….. A. 1CC90H B. E023H C. 3F12DH D. 3F12CH 83. The memory location addressed by the DS = 1239H and EBX = 0000A900H real mode register combinations is A. 1CC91H B. 1CC90H C. 3F12DH D. BB39H 84. What do the MOV AX, BX instruction accomplish? A. copy AX into BX B. copy BX into AX C. delete the contents of BX D. keep the contents of AX unchanged  @DU Helpers 2021 85. What do the MOV SP, BP instruction accomplish? A. copy BP into SP B. copy SP into BP C. delete the contents of BP D. keep the contents of SP unchanged 86. Select an instruction for the copy DS into AX task A. MOV DS B. MOV DS, AX C. MOV AX, DS D. MOV AX 87. Select an instruction for the move 123AH into AX task A. MOV 123AH B. MOV AX C. MOV 123AH, AX D. MOV AX, 123AH 88. If the base pointer (BP) addresses memory, the contains the data A. Stack segment (SS) B. Data segment (DS) C. Code segment (CS) D. Extra segment (EX) 89. If the base register (BX) addresses memory, the contains the data A. Stack segment (SS) B. Data segment (DS) C. Code segment (CS) D. Extra segment (EX) 90. If the instruction pointer (IP) addresses memory, the contains the data A. Stack segment (SS) B. Data segment (DS) C. Code segment (CS) D. Extra segment (EX) 91.Which of the following instruction is not valid? A. MOV AX, BX B. MOV CX, AL C. MOV AX, 5000H D. PUSH AX 92. In 80386 and above, the ECX register consists of …………………… A. 8-bit B. 32-bit C. 16-bit D. 64-bit 93.How many bytes are popped from the stack by a POP EBX? A. 2 bytes B. 4 bytes C. 3 bytes D. 32 bytes 94.How many bytes are stored on the stack by a PUSH AX? A. 2 bytes B. 4 bytes C. 16 bytes D. 1 bytes  @DU Helpers 2021 95. The stack is …............. memory A. FIFO (First in First out) B. LIFO (Last in First out) C. FILO (First in Last out) D. LILO (Last in Last out) 96. Whenever a word of data is pushed onto the stack, the high-order 8 bits are placed in the location addressed by…………. A. SP B. SP-1 C. SP-2 D. SP+1 97. Whenever data is popped from the stack, the low-order 8 bits are removed from the location addressed by………. A. SP B. SP-1 C. SP-2 D. SP+1 98. Whenever a word of data is pushed onto the stack, the loworder 8 bits are placed in the location addressed by…………… A. SP B. SP-1 C. SP-2 D. SP+1 99. Whenever data is popped from the stack, the high-order 8 bits are removed from the location addressed by…………….. A. SP B. SP-1 C. SP-2 D. SP+1 100. If you want to jump to the location address by register BX, you will write………. A. JMP [BX] B. JMP BX C. CALL [BX] D. CALL BX 101. To add the contents of register AX with BX and store the addition into AX, you will write the instruction …………………… A. ADC AX, BX B. ADD BX, AX C. ADD AX, BX D. ADC BX, AX 102. To add with carry the contents of register CX with BX and store the result into BX, you will write the instruction …………………… A. ADC CX, BX B. ADD BX, CX C. ADD CX, BX D. ADC BX, CX 103. The INC instruction …............ the content of the destination by 1 A. increment B. decrement C. Subtract D. Divide  @DU Helpers 2021 104. This type of addition is not allowed A. register to memory B. memory to memory C. memory to register D. register to register 105. The instruction ADD BX, 245FH is an example of……………… A. register to memory addition B. memory to memory addition C. memory to register addition D. immediate addition 106. The arithmetic instruction used to add AL to the byte contents of the data segment memory location addressed by BX with the sum stored in the same memory location is……………….. A. ADD AL, [BX] B. ADD BX, AL C. ADD [BX], AL D. ADD AL, BX 107. The arithmetic instruction used to add CL to the byte contents of the stack segment memory location addressed by BP with the sum stored in CL is………….. A. ADD CL, [BP] B. ADD [BP], CL C. ADD [BP], [CL] D. ADD [CL], [BP] 108. To subtract the contents of register AX from BX and store the result into AX, you will write the instruction …………………… A. SUB AX, BX B. SBB AX, BX C. SUB BX, AX D. SBB BX, AX 109. To subtract with borrow the contents of register CX from BX and store the result into BX, you will write the instruction …………………… A. SUB CX, BX B. SBB BX, CX C. SUB BX, CX D. SBB CX, BX 110. The DEC instruction …............... the content of the destination by 1 A. increment B. decrement C. Add D. Divide 111. The arithmetic instruction used to subtract AX from the word contents of the data segment memory location addressed by DI+2 with the difference stored in the same memory location is……………….. A. SUB [DI], AX B. SUB AX, [DI+2] C. SUB [DI+2], AX D. SUB AX, [DI] 112. The arithmetic instruction used to subtract CX to the word contents of the stack segment memory location addressed by BP-1 with the difference stored in CX is…………. A. SUB CX, [BP] B. SUB CX, [BP-1] C. SUB [BP], CX D. SUB [BP-1], CX  @DU Helpers 2021 113. The comparison instruction CMP is a subtraction instruction that …………... A. change the destination and Flag bits B. change only the destination C. change only the Flag bits D. doesn’t change the destination nor Flag bits 114. The arithmetic instruction used to subtract AX from the word contents of the data segment memory location addressed by DI is………………... A. SUB [DI], AX B. CMP [DI], AX C. SUB AX, [DI] D. CMP AX, [DI] 115. The arithmetic instruction used to subtract BX from AX is………………... A. CMP AX, BX B. SUB AX, BX C. SUB BX, AX D. CMP BX, AX 116. IMUL instruction is a signed ……………… A. Division B. Multiplication C. Addition D. Subtraction 117. DIV instruction is unsigned ………………... A. Division B. Multiplication C. Addition D. Subtraction 118. If two 8-bit numbers are multiplied, this generate ……………….. A. 8-bit product B. 32-bit product C. 16-bit product D. 64-bit product 119. If two 16-bit numbers are multiplied, this generate ………………... A. 8-bit product B. 32-bit product C. 16-bit product D. 64-bit product 120. If two 16-bit numbers are multiplied, the product appears in ………………... A. AX B. DX-AX C. AX-DX D. DX 121. If two 8-bit numbers are multiplied, the product appears in ………………... A. AX B. DL-AL C. AL-DL D. AL 122. What does the MUL CL instruction mean? A. AX is multiplied with CL, the signed product in DX-AX. B. AL is multiplied with CL, the signed product in AX. C. AL is multiplied with CL, the unsigned product in AX. D. AX is multiplied with CL, the signed product in DX-AX.  @DU Helpers 2021 123. What does the IMUL CX instruction mean? A. AX is multiplied with CX, the signed product in DX-AX. B. AL is multiplied with CX, the signed product in AX. C. AL is multiplied with CX, the unsigned product in AX. D. AX is multiplied with CX, the unsigned product in DX-AX. 124. The arithmetic instruction used to multiply AL to the byte contents of the data segment memory location addressed by BX with the signed product in AX is……………….. A. MUL BYTE PTR [BX] B. IMUL BYTE PTR [BX] C. MUL WORD PTR [BX] D. IMUL WORD PTR [BX] 125. The arithmetic instruction used to multiply AX to the word contents of the data segment memory location addressed by SI with the unsigned product in DX-AX is………………... A. MUL BYTE PTR [SI] B. IMUL BYTE PTR [SI] C. MUL WORD PTR [SI] D. IMUL WORD PTR [SI] 126. What does the IDIV CL instruction mean? A. AX is divided by CL, unsigned quotient in AL and unsigned remainder in AH. B. AX is divided by CL, signed quotient in AL and signed remainder in AH. C. AX is divided by CL, signed quotient in AH and signed remainder in AL. D. AX is divided by CL, signed quotient in AH and signed remainder in AL. 127. What does the DIV SI instruction mean? A. DX-AX is divided by SI, unsigned quotient in AX and unsigned remainder in DX. B. DX-AX is divided by SI, unsigned quotient in AX and unsigned remainder in BX. C. DX-AX is divided by SI, unsigned quotient in DX and unsigned remainder in AX. D. DX-AX is divided by SI, unsigned quotient in DX and unsigned remainder in BX. 128. The arithmetic instruction used to divide AX by the byte contents of the stack segment memory location addressed by BP with the signed quotient in AL and the signed remainder in AH is………………... A. DIV BYTE PTR [BP] B. IDIV BYTE PTR [BP] C. DIV WORD PTR [BP] D. IDIV WORD PTR [BP] 129. The arithmetic instruction used to divide DX-AX by the word contents of the stack segment memory location addressed by BP with the unsigned quotient in AX and the unsigned remainder in DX is………………... A. DIV BYTE PTR [BP] B. IDIV BYTE PTR [BP] C. DIV WORD PTR [BP] D. IDIV WORD PTR [BP] 130. ………………… affect the flag register A. Only Arithmetic instructions B. Only Logic instructions C. Neither Arithmetic nor logic instructions D. Arithmetic and logic instructions 131. The TEST instructions is a special type of AND instruction that ………………… A. change the destination and Flag bits B. change only the destination C. change only the Flag bits D. doesn’t change the destination nor Flag bits  @DU Helpers 2021 132. Which statement is true concerning NOT instruction and NEG instruction? A. NEG is logic instruction but NOT is arithmetic instruction. B. NOT is logic instruction but NEG is arithmetic instruction. C. They are both arithmetic instructions. D. They are both logic instructions. 133. If register AL = 01010010B, the value of the register after NEG AL instruction will be………… A. 10101101 B. 10101110 C. 1010010 D. 1010011 134. If DX = AAAAH, SI = 0100, DS: 100H = 0FH, DS: 101H = F0H, the results produced in the destination operand after executing AND DX, [SI] instruction is….………… A. AAAAH B. A00AH C. F00FH D. 00FFH 135. If AX = 5555H, BX = 0010H, DI = 0200, DS: 210H = AAH, DS: 211H = AAH, the results produced in the destination operand after executing OR [BX+DI], AX instruction is….………… A. FFFFH B. AAAAH C. 5555H D. 00FFH 136. If AX = 5555H, BX = 0010H, SI = 0100, DS: 110H = 00H, DS: 111H = FFH, the results produced in the destination operand after executing XOR AX, [SI+BX] instruction is….………… A. 55AAH B. AA55H C. 5555H D. FF00H 137. If DS: 300H = AAH, DS: 301H = FFH, the results produced in the destination operand after executing NOT [0300H] instruction is….………… A. FCFFH B. 0505H C. 5500H D. 55H 138. What does the SHR ECX, 10 instruction mean? A. ECX is logically shifted right 10 places B. ECX is logically shifted left 10 places C. ECX is arithmetically shifted right 10 places D. ECX is arithmetically shifted left 10 places 139. To arithmetically shift left the register BX five places, the instruction will be………… A. SAR BX, 5 B. SHR BX, 5 C. SAL BX, 5 D. SHL BX, 5 140. What does the RCL BL, 6 instruction mean? A. BL rotate left 6 places B. BL rotate right through carry 6 places C. BL rotate left through carry 6 places D. BL rotate right 6 places  @DU Helpers 2021 141. To rotate right register AH through carry the number of places specified in CL, the instruction will be………… A. RCR AH, CL B. RCR CL, AH C. ROR AH, CL D. ROR CL, AH 142. What does the ROR EDX, 18 instruction mean? A. EDX rotate left 18 places B. EDX rotate right through carry 18 places C. EDX rotate left through carry 18 places D. EDX rotate right 18 places 143. The size of opcode field in machine language is …………………… A. 1-byte long B. 2-bytes long C. either 1 or 2 bytes long D. 3-bytes long 144. In the general form of the first opcode byte of machine language instruction, if the direction bit D = 1, this mean ….. A. Transfer to register B. Transfer from register C. Indicate word D. Indicate byte 145. In the general form of the first opcode byte of machine language instruction, if the direction bit D = 0, this mean ….. A. Transfer to register B. Transfer from register C. Indicate word D. Indicate byte 146. In the general form of the first opcode byte of machine language instruction, if the word bit W = 1, this mean ……… A. Transfer to register B. Transfer from register C. Indicate word D. Indicate byte 147. In the general form of the first opcode byte of machine language instruction, if the direction bit W = 0, this mean …. A. Transfer to register B. Transfer from register C. Indicate word D. Indicate byte 148. If the mode field contains 11, this mean …………………… A. No displacement B. it selects the register-addressing mode C. it select data memory addressing mode D. 16-bit signed displacement 149. If the mode field contains 00, this mean …………………… A. No displacement B. it selects the registeraddressing mode C. it select data memory addressing mode D. 16-bit signed displacement  @DU Helpers 2021 150. If the mode field contains 10, this mean …………………… A. No displacement B. it selects the registeraddressing mode C. 8-bit signed extended displacement D. 16-bit signed displacement 151. If the mode field contains 01, this mean …………………… A. No displacement B. it selects the register-addressing mode C. 8-bit signed extended displacement D. 16-bit signed displacement 152. If you have a machine language instruction 8A15H, the corresponding assembly language instruction is …………… A. MOV [DI], DL B. MOV DL, [DI] C. MOV [DI], DI D. MOV [DL], DL 153. If you have a machine language instruction 8BECH, the corresponding assembly language instruction is …………… A. MOV BP, SP B. MOV SP, BP C. MOV [BP], SP D. MOV [SP], BP 154. If you have an assembly language instruction Mov SI, [BX+2], the corresponding machine language instruction is A. 8B77H B. 8A7702H C. 8B7702H D. 8A77H 155. If you have an assembly language instruction Mov [BX+4], DI, the corresponding machine language instruction is …………………… A. 897FH B. 887F04H C. 8B7704H D. 897F04H 156. Suppose that DS=1000H, SS=2000H, BP=1500H, BX=0100, and SI=0200H. Determine the address accessed by MOV [SI+100H], EAX, assuming real mode operation A. 20400H B. 10300H C. 10400H D. 20300H  @DU Helpers 2021 157. If you have an assembly language instruction Mov [BX+4], DI, the corresponding machine language instruction is …………………… A. 8B7704H B. 897FH C. 887F04H D. 897F04H 158. If you have a machine language instruction 8A5501H, the corresponding assembly language instruction is …………………… A. MOV [DI], DL B. MOV DL, [DI+1] C. MOV [DI+1], DL d. MOV DL, [DI] D. MOV DL, [DI]