Von Neumann Architecture PDF

From the concept of the Von Neumann architecture we have gotten 3 key concepts: - Data and instructions are stored in a single read/write memory - The contents of this memory are addressed by their location - Executions are carried out in a sequential manner. A program is a sequence of ste...

From the concept of the Von Neumann architecture we have gotten 3 key concepts: - Data and instructions are stored in a single read/write memory - The contents of this memory are addressed by their location - Executions are carried out in a sequential manner. A program is a sequence of steps, for each step, an operation is executed and for each operation a different set of control signals are required. The CPU exchanges data with memory by mainly using 2 registers: - MAR: this stores the address of the data going to be used by the MBR. - MBR: this stores the data to be written in /read from memory. The I/O address register (I/O AR) specifies a particular I/O device, and the I/O buffer register (I/OBR) is used for the exchange of data between an I/O module and the CPU. The I/O module facilitates communication with external devices. The memory module consists of locations numbered by their addresses, and contains data in the locations. The instruction cycle is the processing required for a single instruction. It contains 2 main tasks, fetching and executing. This brings about the fetch and execute cycle.  Fetch cycle: The processor fetches the instruction from memory and the PC holds the address of the next instruction to be fetched. The program counter is incremented, unless told otherwise. The fetched instruction is loaded into the IR and the instruction is executed by the processor. Instruction cycle: the instructions executed by the processor can be categorized into 4: - Processor-memory: data transfer between CPU and main memory - Processor-I/O: Data transfer between CPU and I/O module - Data processing: The processor may perform some arithmetic or logic operation on data. - Control: The sequence of executions could be altered. An instruction may be required to combine all the 4. For example, the processor may fetch an instruction from location 149, which specifies that the next instruction be from location 182. The processor will remember this fact by setting the program counter to 182. Thus, on the next fetch cycle, the instruction will be fetched from location 182 rather than 150. This is an example of a program being executed: Hexadecimal notation is used when representing the contents of memory and registers. This program is trying to add the contents of address 940 and 941, then display the result in address 941. - In the first step, the PC contains 300, this shows that the address of the first instruction to be executed is in address 300. The instruction (1940) is loaded into the IR and the PC is incremented by 1. - In the second step, the first number in the IR (1) shows that the AC is to be loaded. The rest of the numbers (940) indicate the address of the information to be loaded. - In the third step, the first instruction has been executed so the next instruction is to be executed. The PC contains 301, the information in address 301 is loaded into the IR (5941) and the PC is incremented. - In the fourth step, the new information (2) is added to the previous information (3) and displays the answer in the AC. - In the fifth step, the PC contains 302 so the information in that address is loaded into the IR and the PC is incremented by 1. - In the sixth step, the information in the AC (5) is stored in address 941 The instruction cycle consists of several states that facilitate the execution of instructions within a processor. These states include: Instruction Address Calculation: calculates the address of the next instruction. Instruction Fetch: fetches instruction from memory. Instruction Operation Decoding: analyses the information to determine the operations and operands required. Operand Address Calculation: determines the address of the operands if needed. Operand Fetch: fetches operands from memory or I/O. Data Operation: performs the operation. Operand Store: writes the result into memory or out to the I/O. The cycle begins with calculating the address of the next instruction, followed by fetching the instruction from memory, decoding it, and determining operand addresses if needed. The processor then fetches operands, performs the specified operation, and stores the results. The diagram illustrates that some states may be null or revisited, and it accommodates multiple operands and results. Interrupts are mechanisms in computers that allow other modules to interrupt the normal processing of a processor. They improve the efficiency of the processor, as external devices operate slower than the processor. Without these interrupts, the processor would remain idle which will cause inefficiency. There are 4 types of interrupts: Program: caused due to an instruction execution Timer: caused by a timer in the processor I/O: caused by an I/O controller Hardware failure: caused by a failure I/O programs are system utilities that perform the I/O operations. It consists of 3 sections: - A sequence of instructions to prepare for the operation. - Carrying out the I/O operation. - A sequence of instructions to complete the operation.  In the diagram with the interrupts, the user programs runs the segments of code. When the WRITE call is made, the I/O program is invoked and the set of codes are carried out. When the I/O command is made, control returns to the user program **WHILE** the I/O command is being executed. When the I/O command has been executed and is now ready to accept more data, an interrupt request signal is sent and the processor stops and saves the current operation. It then allows an interrupt handler to service the interrupt. It then continues the operation that it had stopped. This is repeated throughout for every instance there is an interrupt. Here it truly shows how interrupts improve efficiency. Using interrupts a new information cycle is generated. In this cycle, after fetching and execution the processor checks if there are any interrupts pending. If there aren\'t any, the processor goes back to the fetch cycle and the cycle continues again. If there was an interrupt, it saves and suspends the execution of the current program, sets the PC to the starting address of an interrupt handler routine. When completed, the processor resumes the suspended program. When dealing with multiple interrupts, there are 2 ways in which they can be dealt with: - Disable any interrupts while an interrupt is being processed: this means that the processor will ignore the interrupt request signal. The interrupt will remain pending until the current interrupt is processed. - Define priorities: this means that the low priority interrupts can interrupt themselves when a higher priority interrupt request signal is detected. When the higher priority interrupt has been processed the lower priority interrupt is resumed. An I/O module can exchange data with the processor. A computer consists of three basic set of components: - The processor - Memory - I/O The interconnection structure is the collection of paths connecting these components. The memory module consists of words of equal length each assigned a unique address. The words can be read from or written into the memory. The location of the operation is specified by an address. The I/O module controls external devices in which each device has a port with a unique address. It can also send interrupt signals to the processor. The processor executes instructions, processes data, controls system operations and receive interrupt signals. The interconnection structure should support data transfer between the memory and processor, I/O and processor, and I/O and memory A bus is a communication pathway connecting two or more devices. Any transmission done by the bus is received by all the devices linked by it, and only one device can transmit data via the bus at a time. It consists of multiple communication lines. The system bus connects the processor, memory and I/O together. For every bus, the lines can be classified into 3 groups and for each bus, the number of lines it contains is the width of the bus. Each line can only carry one bit at a time. - Data lines: they carry data among the system modules. When compiled is called the data bus. The width of this bus indicates how many bits the bus can transfer at a time. - Address lines: they identify the source and destination of data. When compiled is called the address bus. The width of this bus shows the maximum memory capacity of the system. - Control lines: they carry out the control and timing of information. These include memory R/W signals, I/O R/W signals, bus request/grant, interrupt requests and clock signals. Many devices being connected onto one bus would lead to propagation delay. There are 2 types of buses Dedicated: there are separate data and address lines Multiplexed: the lines are shared, it contains less lines, but is more complex and lower performance than dedicated. Bus arbitration is the process which determines who gets control of the bus, ensuring only one module gets access at a time There are 2 types of arbitration Centralized: a single central device decides which module gets control of the bus. Distributed: each modules take part in deciding who should get control of the bus Timing is the synchronization of different events that occur on the bus to ensure smooth communications. Synchronous timing is where events are determined by clock signals. The control bus includes a clock line which allows all devices to synchronize with the clock. All events take place in a single clock cycle. Status lines indicate the current status of the bus, whether a read or write will occur. The read cycle is the process where data lines carry data from memory to the CPU. The write cycle is the process where data lines carry data from the CPU to the memory. Asynchronous timing is where the occurrence of events don't rely on a clock signal, rather depends on the occurrence of the previous event. Events wait on the previous event to be executed before proceeding to assure synchronization. In asynchronous timing (read), the read signal is sent to initiate data retrieved from memory. After being processed, the data is placed onto the data lines and then an acknowledgement signal is sent to confirm that data has been successfully read. In asynchronous timing (write), the write signal is activated to begin the write operation instructing the system to store the data in the given address. An acknowledgement signal is sent to confirm that data has been successfully written. These are the differences between the 2 types of timing:  PCI bus: peripheral component interconnection. It is a standard developed by Intel and operates in either 32 or 64 bit with 50 lines, it is used to connect hardware devices in a computer. Compared to other bus specifications, PCI delivers better system performance. PCI requires some lines for it to function, these include: - System lines which handle central operations. - Address and data lines which transmit address and data. - The interface control which manages the control interface between devices - Arbitration - Error lines used to signal errors during PCI operation PCI commands are transactions between the initiator (master) and target. The master gains control of the bus, then determines the type of operation. The address phase specifies the address of the data being accessed. The PCI bus arbiter manages control of the PCI bus. Each PCI device can request for access to control the bus and the arbiter decides and grants access to the device most suitable.