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ECE-2124 Digital System Design Dr. Arjun Sunil Rao Dr. Arjun Sunil Rao, Department Department ofof Electronics Electronics and Communication...

ECE-2124 Digital System Design Dr. Arjun Sunil Rao Dr. Arjun Sunil Rao, Department Department ofof Electronics Electronics and Communication & Communication Engineering, Engineering, MIT, Manipal MIT Manipal  Pre-requisites Basic Electronics subject: ❖ Number systems and codes ❖ Boolean algebraic theorems ❖ Simplification of Boolean expressions ❖ Logic gates ❖ Concept of Universal Logic ❖ Flip flops Dr. Arjun Sunil Rao, Department Department ofof Electronics Electronics and Communication & Communication Engineering, Engineering, MIT, Manipal MIT Manipal  Reference Books 1. Donald D.Givone, “Digital Principles and Design”, Tata McGraw Hill, 2002. 2. William I. Fletcher, “An Engineering approach to Digital Design”, Prentice Hall of India, 2009. 3. Zvi Kohavi, Niraj K Jha, “Switching and Finite Automata Theory”, Cambridge, Third edition, 2010. 4. Samir Palnitkar, “Verilog HDL: A Guide to Digital Design and Synthesis,” Prentice Hall PTR, 2003. 5. Charles Roth, Lizy Kurian John, Byeong Kil Lee, Digital System Design Using Verilog, 1st Edition, 2016. *https://edaplayground.com/ 6. M. Morris Mano, Morris M Mano - Digital Design (3rd Edition) Dr. Arjun Sunil Rao, Department Department ofof Electronics Electronics and Communication & Communication Engineering, Engineering, MIT, Manipal MIT Manipal  Analog vs Digital systems https://www.youtube.com/watch?v=btgAUdbj85E https://www.youtube.com/watch?v=j7-acuTio4M https://www.youtube.com/watch?v=WxJKXGugfh8 Dr. Arjun Sunil Rao, Department Department ofof Electronics Electronics and Communication & Communication Engineering, Engineering, MIT, Manipal MIT Manipal  Digital Systems Advantages of Digital System: o Digital circuits are easy to design and cheaper than analog circuits. o The hardware implementation in digital circuits, is more flexible than analog. o The effect of distortion, noise, and interference is much less in digital signals as they are less affected. o Reproducibility of the results and accuracy. o Integration of circuits becomes more economical. Disadvantages of Digital System: o Sampling error o Digital communication require greater bandwidth Dr. Arjun Sunil Rao, Department Department ofof Electronics Electronics and Communication & Communication Engineering, Engineering, MIT, Manipal MIT Manipal  Applications of Digital Systems ▪ Camera ▪ TV ▪ Electronic calculators ▪ Phone ▪ Computer ▪ Audio/ Image/ Video processing ▪ Flash drive ▪ Scanner ▪ Printer ▪ E-readers ▪ Watch Dr. Arjun Sunil Rao, Department Department ofof Electronics Electronics and Communication & Communication Engineering, Engineering, MIT, Manipal MIT Manipal  Introduction Digital gates have one or more inputs and produce an output that is a function of the current input values. All inputs and output can take the values 0 or 1 only. A gate is called a combinational circuit because the output only depends on the current input combination. Digital circuits are created by using a number of connected gates. Digital or logic design is concerned with the design of such circuits. Dr. Arjun Sunil Rao, Department Department ofof Electronics Electronics and Communication & Communication Engineering, Engineering, MIT, Manipal MIT Manipal  Binary Logic Definition of Binary Logic: I. Binary logic consists of binary variables and a set of logical operations. II. The variables are designated by letters of the alphabet, such as A, B, C, x, y, z, etc, with each variable having two and only two distinct possible values: 1 and 0, III. Three basic logical operations: AND, OR, and NOT. Dr. Arjun Sunil Rao, Department Department ofof Electronics Electronics and Communication & Communication Engineering, Engineering, MIT, Manipal MIT Manipal  Basic Gates Dr. Arjun Sunil Rao, Department Department ofof Electronics Electronics and Communication & Communication Engineering, Engineering, MIT, Manipal MIT Manipal  Universal Gates Dr. Arjun Sunil Rao, Department Department ofof Electronics Electronics and Communication & Communication Engineering, Engineering, MIT, Manipal MIT Manipal  Logic Gates Dr. Arjun Sunil Rao, Department Department ofof Electronics Electronics and Communication & Communication Engineering, Engineering, MIT, Manipal MIT Manipal Basic Laws of Boolean algebra Department of Electronics & Communication Engineering, MIT, Manipal  Basic Laws of Boolean algebra Dr. Arjun Sunil Rao, Department Department ofof Electronics Electronics and Communication & Communication Engineering, Engineering, MIT, Manipal MIT Manipal  Basic Laws of Boolean algebra Dr. Arjun Sunil Rao, Department Department ofof Electronics Electronics and Communication & Communication Engineering, Engineering, MIT, Manipal MIT Manipal  Basic Laws of Boolean algebra Dr. Arjun Sunil Rao, Department Department ofof Electronics Electronics and Communication & Communication Engineering, Engineering, MIT, Manipal MIT Manipal  Basic Laws of Boolean algebra Dr. Arjun Sunil Rao, Department Department ofof Electronics Electronics and Communication & Communication Engineering, Engineering, MIT, Manipal MIT Manipal  Dual of Boolean expression The Dual of any expression can be obtained easily by the following rules. 1. Change all 0’s to 1’s 2. Change all 1’s to 0’s 3. AND’s (dot’s) are replaced by OR’s (plus) 4. OR’s (plus) are replaced by AND’s (dot’s) Dr. Arjun Sunil Rao, Department Department ofof Electronics Electronics and Communication & Communication Engineering, Engineering, MIT, Manipal MIT Manipal  1. Change all 0’s to 1’s 2. Change all 1’s to 0’s 3. AND’s (dot’s) are replaced by OR’s (plus) 4. OR’s (plus) are replaced by AND’s (dot’s) 1. Find the dual of Boolean expression AB+A’C+BC= AB+A’C Solution: (A+B)(A’+C)(B+C)=(A+B)(A’+C) 2. (A+B+C)(A+B’)=0 Solution: ABC + AB’=1 Dr. Arjun Sunil Rao, Department Department ofof Electronics Electronics and Communication & Communication Engineering, Engineering, MIT, Manipal MIT Manipal  De Morgan’s Theorems Dr. Arjun Sunil Rao, Department Department ofof Electronics Electronics and Communication & Communication Engineering, Engineering, MIT, Manipal MIT Manipal  De Morgan’s Theorems Dr. Arjun Sunil Rao, Department Department ofof Electronics Electronics and Communication & Communication Engineering, Engineering, MIT, Manipal MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal  IMPLEMENTATION OF BOOLEAN EXPRESSION USING LOGIC GATES Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal  IMPLEMENTATION OF BOOLEAN EXPRESSION USING UNIVERSAL GATES Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal  Implement the following Boolean Expression using NAND only. Y= A’+BC’ Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal  Implement the following Boolean Expression using NAND only. Y=A+[(AB)+(C+D)] Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal  Implement the following Boolean Expression using NOR only. Y= A’+BC’ Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal  Implement the following Boolean Expression using NAND only. Y=A+[(AB)+(C+D)] Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal  =(A+B+CC’)(AA’+B+C)+(A+BB’+C) =(A+B+C)(A+B+C’)(A+B+C)(A’+B+C)(A+B+C)(A+B’+C) =(A+B+C)(A+B+C’)(A’+B+C)(A+B’+C) Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal  Small letter m indicates minterms) Put 1 in designated places Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal  Capital letter M indicates maxterms) Put 0 in designated places Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal  Don’t Care Condition: Certain inputs never occur in normal operation. i.e., corresponding output for a combination never occurs. X is the don’t care condition. It is neither ‘1’ nor ‘0’. Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal  Design a logic circuit that generates an output low for the inputs 0000 to 1000, high for the input entry 1001, and ‘X’ factor for 1010 through 1111. Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal  Variable Entered Map or VEM Technique Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal  1 1 Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal  3 variable Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal  Code types BCD-Binary Coded Decimal ASCII (American Standard Code for Information Interchange) Gray Code Excess-3 (XS-3) Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal  Binary to BCD conversion Don’t care terms Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Binary to Gray Code: Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal  Binary to Gray Code: Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Gray Code to Binary Conversion: Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal  BCD to 8 4 -2 -1 code converter W = A+BD+BC X= B’D+B’C’+BCD Y=C’D+CD’ Z=D Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal  8 4 -2 -1 code to BCD converter Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal  BCD to EXCESS-3 Code Conversion BCD + addition of 3 1 0 0 1 is 10th combination Digits more than 11 to 16 are considered as don’t cares in the conversion. If a carry is present in the addition. Add another 0011 (3) to the added output. Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal  0 1 2 3 4 5 6 7 8 9 Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal  Logic diagram for W, X, Y and Z Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal  Parity generator and checker Why should we study Parity generator and checker? This is a combinational circuit Communication channel Two types of parity generators: 1. ODD parity generator Transmitter Receiver 2. EVEN parity generator 2-bit ODD parity generator A B P 0 0 1 A 2 bit ODD P 0 1 0 B PG 1 0 0 1 1 1 Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal  Parity generator and checker (cont’d) Parity checker Communication A B P e channel 0 0 0 1 Transmitter Receiver 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 Table from previous slide 1 1 1 0 A B P 0 0 1 0 1 0 1 0 0 1 1 1 Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal 1 1 1 1 1 Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal  1 1 1 1 1 Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal  Full subtractor using half subtractor Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal  Implement using universal Gates: Half Adder Half Subractor Full adder Full subtractor Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal  4-bit Binary Adder/Parallel Adder/ Ripple Carry Adder Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal  4 bit BCD adder Case 1: When sum is less than 1001 (decimal 9) A 0 0 0 1 1 B 0 0 1 1 3 Sum 0 1 0 0 4 Case 2: when sum is between 1001 Converting invalid BCD to valid BCD and 1111 (between 10 and 15) 1 1 0 0 12 1 1 1 0 1 1 0 6 A 0 1 1 1 7 1 0 0 1 0 B 0 1 0 1 5 1 2 Valid Sum 1 1 0 0 12 (invalid BCD ) BCD  Case 3: When sum is more than 1111 (decimal 15) 1 0 0 1 9 + 1 0 0 0 8 1 0 0 0 1 17 (invalid BCD) + 0 1 1 0 6 1 0 1 1 1 1 7 Valid BCD Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal  Sum in decimal Cout S3 S2 S1 S0 0 0 0 0 0 0 1 0 0 0 0 1 2 0 0 0 1 0 3 0 0 0 1 1 4 0 0 1 0 0 5 0 0 1 0 1 6 0 0 1 1 0 7 0 0 1 1 1 8 0 1 0 0 0 9 0 1 0 0 1 10 0 1 0 1 0 11 0 1 0 1 1 12 0 1 1 0 0 Invalid BCD 13 0 1 1 0 1 14 0 1 1 1 0 15 0 1 1 1 1 16 1 0 0 0 0 17 1 0 0 0 1 18 1 0 0 1 0 19 1 0 0 1 1 Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal  Cout S3 S2 S1 S0 F 10 0 1 0 1 0 1 11 0 1 0 1 1 1 12 0 1 1 0 0 1 13 0 1 1 0 1 1 14 0 1 1 1 0 1 15 0 1 1 1 1 1 With Cout Cout Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal  Cout Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal  Ripple Adder Delay Assume gate delay = T 8 T to compute the last carry Total delay = 8 + 1 = 9T 1 delay form first half adder Delay = (2n+1)T How to improve? Src: Course CD Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal  Carry look ahead (CLA) adder Parallel adder B1 A1 C0 C1 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1  Excess-3 addition Non weighted Sequential Self-complimentary XS-3 0 1 0 1 Decimal=2 9’s 1 0 1 0 Decimal = 7 compliment 9-7=2 (original number) Rules of Excess 3 addition: Rule 1: If any carry occurs, add 3 (0011). Rule 2: It carry doesn’t occurs, subtract 3 (0011). Example for Rule 2 (No carry is generated) A is BCD number, A+0011 is XS-3 code A+0011 B is BCD number, B+0011 is XS-3 code B+0011 C is BCD number i.e., sum of A and B C+0110 -0011=C+0011 Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal  For example, 6+3: 1 0 0 1 + 0 1 1 0 No carry 1 1 1 1 - 0 0 1 1 Ans: 1 1 0 0 For example, 7+3=10. Inputs: 1 digit. Output: 2 digit Hence, 07+03 07 0 0 1 1 1 0 1 0 03 0 0 1 1 0 1 1 0 Sum 0 1 1 1 0 0 0 0 No carry Carry 0 1 1 1 0 0 0 0 - 0 0 1 1 0 0 1 1 + 0 1 0 0 0 0 1 1 =10 Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal  For A=B Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal  For A>B Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal  For AB Dr. Arjun Sunil Rao, Department of Electronics and Communication Engineering, MIT Manipal  For A